PWM Simulation Results

Wednesday January 17 2024 20:02:30 UTC

GitHub Revision: 4d88b9516c

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 3635458896929517279689574864899235923834879224879080668186365324190153451241

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 10.000s 5.630ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 4.000s 17.287us 5 5 100.00
V1 csr_rw pwm_csr_rw 15.000s 23.263us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 11.000s 2.247ms 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 4.000s 124.531us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 7.000s 24.478us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 15.000s 23.263us 20 20 100.00
pwm_csr_aliasing 4.000s 124.531us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.117m 116.638ms 50 50 100.00
V2 pulse pwm_rand_output 1.117m 116.638ms 50 50 100.00
V2 blink pwm_rand_output 1.117m 116.638ms 50 50 100.00
V2 heartbeat pwm_rand_output 1.117m 116.638ms 50 50 100.00
V2 resolution pwm_rand_output 1.117m 116.638ms 50 50 100.00
V2 multi_channel pwm_rand_output 1.117m 116.638ms 50 50 100.00
V2 polarity pwm_rand_output 1.117m 116.638ms 50 50 100.00
V2 phase pwm_rand_output 1.117m 116.638ms 50 50 100.00
V2 lowpower pwm_rand_output 1.117m 116.638ms 50 50 100.00
V2 perf pwm_perf 57.000s 45.649ms 49 50 98.00
V2 stress_all pwm_stress_all 5.433m 154.166ms 50 50 100.00
V2 alert_test pwm_alert_test 8.000s 22.948us 50 50 100.00
V2 intr_test pwm_intr_test 8.000s 13.354us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 9.000s 146.091us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 9.000s 146.091us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 4.000s 17.287us 5 5 100.00
pwm_csr_rw 15.000s 23.263us 20 20 100.00
pwm_csr_aliasing 4.000s 124.531us 5 5 100.00
pwm_same_csr_outstanding 8.000s 47.014us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 4.000s 17.287us 5 5 100.00
pwm_csr_rw 15.000s 23.263us 20 20 100.00
pwm_csr_aliasing 4.000s 124.531us 5 5 100.00
pwm_same_csr_outstanding 8.000s 47.014us 20 20 100.00
V2 TOTAL 289 290 99.66
V2S tl_intg_err pwm_tl_intg_err 9.000s 104.862us 20 20 100.00
pwm_sec_cm 8.000s 292.729us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 9.000s 104.862us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 419 420 99.76

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.47 99.48 99.08 99.84 94.96 94.92 -- 100.00 99.34

Failure Buckets

Past Results