PWM Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: 796f9fb805

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 12.000s 3.179ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 5.000s 49.404us 5 5 100.00
V1 csr_rw pwm_csr_rw 7.000s 79.768us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 11.000s 564.729us 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 7.000s 57.974us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 8.000s 15.916us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 7.000s 79.768us 20 20 100.00
pwm_csr_aliasing 7.000s 57.974us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.800m 10.501ms 50 50 100.00
V2 pulse pwm_rand_output 1.800m 10.501ms 50 50 100.00
V2 blink pwm_rand_output 1.800m 10.501ms 50 50 100.00
V2 heartbeat pwm_rand_output 1.800m 10.501ms 50 50 100.00
V2 resolution pwm_rand_output 1.800m 10.501ms 50 50 100.00
V2 multi_channel pwm_rand_output 1.800m 10.501ms 50 50 100.00
V2 polarity pwm_rand_output 1.800m 10.501ms 50 50 100.00
V2 phase pwm_rand_output 1.800m 10.501ms 50 50 100.00
V2 lowpower pwm_rand_output 1.800m 10.501ms 50 50 100.00
V2 perf pwm_perf 53.000s 10.506ms 50 50 100.00
V2 stress_all pwm_stress_all 5.617m 308.334ms 46 50 92.00
V2 alert_test pwm_alert_test 10.000s 35.752us 50 50 100.00
V2 intr_test pwm_intr_test 7.000s 13.938us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 10.000s 442.972us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 10.000s 442.972us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 5.000s 49.404us 5 5 100.00
pwm_csr_rw 7.000s 79.768us 20 20 100.00
pwm_csr_aliasing 7.000s 57.974us 5 5 100.00
pwm_same_csr_outstanding 8.000s 33.621us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 5.000s 49.404us 5 5 100.00
pwm_csr_rw 7.000s 79.768us 20 20 100.00
pwm_csr_aliasing 7.000s 57.974us 5 5 100.00
pwm_same_csr_outstanding 8.000s 33.621us 20 20 100.00
V2 TOTAL 286 290 98.62
V2S tl_intg_err pwm_tl_intg_err 8.000s 1.237ms 20 20 100.00
pwm_sec_cm 6.000s 141.079us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 8.000s 1.237ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 416 420 99.05

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.42 99.38 98.89 99.80 95.00 94.92 -- 100.00 99.34

Failure Buckets

Past Results