PWM Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: `f7fc348358`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	5.000s	2.219ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	21.565us	5	5	100.00
V1	csr_rw	pwm_csr_rw	3.000s	53.878us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	12.000s	2.528ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	5.000s	80.941us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	4.000s	114.364us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	3.000s	53.878us	20	20	100.00
		pwm_csr_aliasing	5.000s	80.941us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	57.000s	131.232ms	50	50	100.00
V2	pulse	pwm_rand_output	57.000s	131.232ms	50	50	100.00
V2	blink	pwm_rand_output	57.000s	131.232ms	50	50	100.00
V2	heartbeat	pwm_rand_output	57.000s	131.232ms	50	50	100.00
V2	resolution	pwm_rand_output	57.000s	131.232ms	50	50	100.00
V2	multi_channel	pwm_rand_output	57.000s	131.232ms	50	50	100.00
V2	polarity	pwm_rand_output	57.000s	131.232ms	50	50	100.00
V2	phase	pwm_rand_output	57.000s	131.232ms	50	50	100.00
V2	lowpower	pwm_rand_output	57.000s	131.232ms	50	50	100.00
V2	perf	pwm_perf	53.000s	42.001ms	50	50	100.00
V2	stress_all	pwm_stress_all	4.767m	251.997ms	48	50	96.00
V2	alert_test	pwm_alert_test	3.000s	37.225us	50	50	100.00
V2	intr_test	pwm_intr_test	3.000s	11.535us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	7.000s	271.112us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	7.000s	271.112us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	21.565us	5	5	100.00
		pwm_csr_rw	3.000s	53.878us	20	20	100.00
		pwm_csr_aliasing	5.000s	80.941us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	108.183us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	21.565us	5	5	100.00
		pwm_csr_rw	3.000s	53.878us	20	20	100.00
		pwm_csr_aliasing	5.000s	80.941us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	108.183us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	pwm_tl_intg_err	5.000s	172.923us	20	20	100.00
		pwm_sec_cm	3.000s	118.922us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	5.000s	172.923us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			418	420	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	6	85.71
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.51	99.48	99.08	99.76	95.34	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

20.pwm_stress_all.77702802335805540833517808112696754531809885777317794038443652741381169266261
Line 524925, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/20.pwm_stress_all/latest/run.log

  UVM_ERROR @ 140449152935 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [5] did not MATCH
  UVM_INFO @ 140449152935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.pwm_stress_all.78629673512059771298966171566503056856761281100325641306056451168191095037867
Line 183242, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/41.pwm_stress_all/latest/run.log

  UVM_ERROR @ 97621221917 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 97621221917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---