PWM Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: e3ca274e77

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 17.000s 1.003ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 8.000s 18.648us 5 5 100.00
V1 csr_rw pwm_csr_rw 3.000s 22.467us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 10.000s 1.307ms 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 5.000s 182.110us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 8.000s 23.206us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 3.000s 22.467us 20 20 100.00
pwm_csr_aliasing 5.000s 182.110us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 59.000s 41.998ms 49 50 98.00
V2 pulse pwm_rand_output 59.000s 41.998ms 49 50 98.00
V2 blink pwm_rand_output 59.000s 41.998ms 49 50 98.00
V2 heartbeat pwm_rand_output 59.000s 41.998ms 49 50 98.00
V2 resolution pwm_rand_output 59.000s 41.998ms 49 50 98.00
V2 multi_channel pwm_rand_output 59.000s 41.998ms 49 50 98.00
V2 polarity pwm_rand_output 59.000s 41.998ms 49 50 98.00
V2 phase pwm_rand_output 59.000s 41.998ms 49 50 98.00
V2 lowpower pwm_rand_output 59.000s 41.998ms 49 50 98.00
V2 perf pwm_perf 53.000s 13.130ms 50 50 100.00
V2 stress_all pwm_stress_all 6.083m 334.214ms 50 50 100.00
V2 alert_test pwm_alert_test 9.000s 164.641us 50 50 100.00
V2 intr_test pwm_intr_test 7.000s 12.498us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 12.000s 46.235us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 12.000s 46.235us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 8.000s 18.648us 5 5 100.00
pwm_csr_rw 3.000s 22.467us 20 20 100.00
pwm_csr_aliasing 5.000s 182.110us 5 5 100.00
pwm_same_csr_outstanding 8.000s 25.192us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 8.000s 18.648us 5 5 100.00
pwm_csr_rw 3.000s 22.467us 20 20 100.00
pwm_csr_aliasing 5.000s 182.110us 5 5 100.00
pwm_same_csr_outstanding 8.000s 25.192us 20 20 100.00
V2 TOTAL 289 290 99.66
V2S tl_intg_err pwm_tl_intg_err 5.000s 1.619ms 20 20 100.00
pwm_sec_cm 16.000s 302.035us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 5.000s 1.619ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 419 420 99.76

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.14 99.24 98.65 99.60 94.35 94.92 -- 100.00 99.01

Failure Buckets

Past Results