PWM Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: `70ad420931`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	10.000s	1.700ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	63.234us	5	5	100.00
V1	csr_rw	pwm_csr_rw	3.000s	40.636us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	10.000s	676.427us	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	80.273us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	8.000s	111.736us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	3.000s	40.636us	20	20	100.00
		pwm_csr_aliasing	4.000s	80.273us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	2.117m	21.881ms	50	50	100.00
V2	pulse	pwm_rand_output	2.117m	21.881ms	50	50	100.00
V2	blink	pwm_rand_output	2.117m	21.881ms	50	50	100.00
V2	heartbeat	pwm_rand_output	2.117m	21.881ms	50	50	100.00
V2	resolution	pwm_rand_output	2.117m	21.881ms	50	50	100.00
V2	multi_channel	pwm_rand_output	2.117m	21.881ms	50	50	100.00
V2	polarity	pwm_rand_output	2.117m	21.881ms	50	50	100.00
V2	phase	pwm_rand_output	2.117m	21.881ms	50	50	100.00
V2	lowpower	pwm_rand_output	2.117m	21.881ms	50	50	100.00
V2	perf	pwm_perf	53.000s	80.769ms	50	50	100.00
V2	stress_all	pwm_stress_all	5.617m	276.085ms	48	50	96.00
V2	alert_test	pwm_alert_test	7.000s	29.118us	50	50	100.00
V2	intr_test	pwm_intr_test	7.000s	21.773us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	8.000s	89.363us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	8.000s	89.363us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	63.234us	5	5	100.00
		pwm_csr_rw	3.000s	40.636us	20	20	100.00
		pwm_csr_aliasing	4.000s	80.273us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	61.530us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	63.234us	5	5	100.00
		pwm_csr_rw	3.000s	40.636us	20	20	100.00
		pwm_csr_aliasing	4.000s	80.273us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	61.530us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	pwm_tl_intg_err	13.000s	154.756us	20	20	100.00
		pwm_sec_cm	3.000s	300.775us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	13.000s	154.756us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			418	420	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	6	85.71
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.62	99.59	99.26	100.00	95.20	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

21.pwm_stress_all.51916195450657541932214378387128632486075903039460622590757287004126653660125
Line 28593, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/21.pwm_stress_all/latest/run.log

  UVM_ERROR @ 43962965105 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [5] did not MATCH
  UVM_INFO @ 43962965105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.pwm_stress_all.93860864781902413689506514166175074223570893038172405242748802863706694591440
Line 748, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/47.pwm_stress_all/latest/run.log

  UVM_ERROR @ 21500676585 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [5] did not MATCH
  UVM_INFO @ 21500676585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---