PWM Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: b111fbcef3

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 6.000s 2.113ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 3.000s 136.505us 5 5 100.00
V1 csr_rw pwm_csr_rw 3.000s 18.886us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 10.000s 7.910ms 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 4.000s 109.358us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 4.000s 48.600us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 3.000s 18.886us 20 20 100.00
pwm_csr_aliasing 4.000s 109.358us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.067m 7.307ms 49 50 98.00
V2 pulse pwm_rand_output 1.067m 7.307ms 49 50 98.00
V2 blink pwm_rand_output 1.067m 7.307ms 49 50 98.00
V2 heartbeat pwm_rand_output 1.067m 7.307ms 49 50 98.00
V2 resolution pwm_rand_output 1.067m 7.307ms 49 50 98.00
V2 multi_channel pwm_rand_output 1.067m 7.307ms 49 50 98.00
V2 polarity pwm_rand_output 1.067m 7.307ms 49 50 98.00
V2 phase pwm_rand_output 1.067m 7.307ms 49 50 98.00
V2 lowpower pwm_rand_output 1.067m 7.307ms 49 50 98.00
V2 perf pwm_perf 51.000s 47.722ms 50 50 100.00
V2 stress_all pwm_stress_all 4.433m 63.511ms 47 50 94.00
V2 alert_test pwm_alert_test 4.000s 34.803us 50 50 100.00
V2 intr_test pwm_intr_test 4.000s 39.784us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 7.000s 479.149us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 7.000s 479.149us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 3.000s 136.505us 5 5 100.00
pwm_csr_rw 3.000s 18.886us 20 20 100.00
pwm_csr_aliasing 4.000s 109.358us 5 5 100.00
pwm_same_csr_outstanding 4.000s 130.438us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 3.000s 136.505us 5 5 100.00
pwm_csr_rw 3.000s 18.886us 20 20 100.00
pwm_csr_aliasing 4.000s 109.358us 5 5 100.00
pwm_same_csr_outstanding 4.000s 130.438us 20 20 100.00
V2 TOTAL 286 290 98.62
V2S tl_intg_err pwm_tl_intg_err 5.000s 372.939us 20 20 100.00
pwm_sec_cm 3.000s 136.772us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 5.000s 372.939us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 416 420 99.05

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 5 71.43
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.15 99.07 98.34 99.76 94.45 94.92 -- 100.00 99.01

Failure Buckets

Past Results