b111fbcef3
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | pwm_smoke | 6.000s | 2.113ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | pwm_csr_hw_reset | 3.000s | 136.505us | 5 | 5 | 100.00 |
V1 | csr_rw | pwm_csr_rw | 3.000s | 18.886us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | pwm_csr_bit_bash | 10.000s | 7.910ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | pwm_csr_aliasing | 4.000s | 109.358us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 4.000s | 48.600us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 3.000s | 18.886us | 20 | 20 | 100.00 |
pwm_csr_aliasing | 4.000s | 109.358us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | dutycycle | pwm_rand_output | 1.067m | 7.307ms | 49 | 50 | 98.00 |
V2 | pulse | pwm_rand_output | 1.067m | 7.307ms | 49 | 50 | 98.00 |
V2 | blink | pwm_rand_output | 1.067m | 7.307ms | 49 | 50 | 98.00 |
V2 | heartbeat | pwm_rand_output | 1.067m | 7.307ms | 49 | 50 | 98.00 |
V2 | resolution | pwm_rand_output | 1.067m | 7.307ms | 49 | 50 | 98.00 |
V2 | multi_channel | pwm_rand_output | 1.067m | 7.307ms | 49 | 50 | 98.00 |
V2 | polarity | pwm_rand_output | 1.067m | 7.307ms | 49 | 50 | 98.00 |
V2 | phase | pwm_rand_output | 1.067m | 7.307ms | 49 | 50 | 98.00 |
V2 | lowpower | pwm_rand_output | 1.067m | 7.307ms | 49 | 50 | 98.00 |
V2 | perf | pwm_perf | 51.000s | 47.722ms | 50 | 50 | 100.00 |
V2 | stress_all | pwm_stress_all | 4.433m | 63.511ms | 47 | 50 | 94.00 |
V2 | alert_test | pwm_alert_test | 4.000s | 34.803us | 50 | 50 | 100.00 |
V2 | intr_test | pwm_intr_test | 4.000s | 39.784us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | pwm_tl_errors | 7.000s | 479.149us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | pwm_tl_errors | 7.000s | 479.149us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 3.000s | 136.505us | 5 | 5 | 100.00 |
pwm_csr_rw | 3.000s | 18.886us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 4.000s | 109.358us | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 4.000s | 130.438us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | pwm_csr_hw_reset | 3.000s | 136.505us | 5 | 5 | 100.00 |
pwm_csr_rw | 3.000s | 18.886us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 4.000s | 109.358us | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 4.000s | 130.438us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 286 | 290 | 98.62 | |||
V2S | tl_intg_err | pwm_tl_intg_err | 5.000s | 372.939us | 20 | 20 | 100.00 |
pwm_sec_cm | 3.000s | 136.772us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 5.000s | 372.939us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 416 | 420 | 99.05 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 7 | 7 | 5 | 71.43 |
V2S | 2 | 2 | 2 | 100.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
98.15 | 99.07 | 98.34 | 99.76 | 94.45 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard]
has 4 failures:
4.pwm_stress_all.13202218699272232626026113192312265576334144493351239617275064207451232484481
Line 872, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/4.pwm_stress_all/latest/run.log
UVM_ERROR @ 177841971014 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [2] did not MATCH
UVM_INFO @ 177841971014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
45.pwm_stress_all.1435707561383719021728481438330031316886998625425345211286547649057217305518
Line 3437587, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/45.pwm_stress_all/latest/run.log
UVM_ERROR @ 119722316041 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [3] did not MATCH
UVM_INFO @ 119722316041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
33.pwm_rand_output.111866666011468807998059688545190126342299108019506651913295619470741485251712
Line 3835029, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/33.pwm_rand_output/latest/run.log
UVM_ERROR @ 7306971553 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [0] did not MATCH
UVM_INFO @ 7306971553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---