PWM Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: 4ee21f808f

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 6.000s 2.206ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 3.000s 55.341us 5 5 100.00
V1 csr_rw pwm_csr_rw 3.000s 18.579us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 9.000s 1.405ms 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 4.000s 194.476us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 4.000s 47.947us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 3.000s 18.579us 20 20 100.00
pwm_csr_aliasing 4.000s 194.476us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.983m 10.945ms 50 50 100.00
V2 pulse pwm_rand_output 1.983m 10.945ms 50 50 100.00
V2 blink pwm_rand_output 1.983m 10.945ms 50 50 100.00
V2 heartbeat pwm_rand_output 1.983m 10.945ms 50 50 100.00
V2 resolution pwm_rand_output 1.983m 10.945ms 50 50 100.00
V2 multi_channel pwm_rand_output 1.983m 10.945ms 50 50 100.00
V2 polarity pwm_rand_output 1.983m 10.945ms 50 50 100.00
V2 phase pwm_rand_output 1.983m 10.945ms 50 50 100.00
V2 lowpower pwm_rand_output 1.983m 10.945ms 50 50 100.00
V2 perf pwm_perf 51.000s 20.588ms 50 50 100.00
V2 stress_all pwm_stress_all 5.350m 74.992ms 49 50 98.00
V2 alert_test pwm_alert_test 4.000s 14.610us 50 50 100.00
V2 intr_test pwm_intr_test 3.000s 11.662us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 6.000s 108.394us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 6.000s 108.394us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 3.000s 55.341us 5 5 100.00
pwm_csr_rw 3.000s 18.579us 20 20 100.00
pwm_csr_aliasing 4.000s 194.476us 5 5 100.00
pwm_same_csr_outstanding 4.000s 105.503us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 3.000s 55.341us 5 5 100.00
pwm_csr_rw 3.000s 18.579us 20 20 100.00
pwm_csr_aliasing 4.000s 194.476us 5 5 100.00
pwm_same_csr_outstanding 4.000s 105.503us 20 20 100.00
V2 TOTAL 289 290 99.66
V2S tl_intg_err pwm_tl_intg_err 6.000s 1.051ms 20 20 100.00
pwm_sec_cm 3.000s 1.155ms 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 6.000s 1.051ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 419 420 99.76

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.50 99.45 99.01 99.92 95.07 94.92 -- 100.00 99.01

Failure Buckets

Past Results