PWM Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: `39211701b5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	14.000s	1.022ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	26.621us	5	5	100.00
V1	csr_rw	pwm_csr_rw	12.000s	29.718us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	10.000s	2.516ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	95.996us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	8.000s	67.683us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	12.000s	29.718us	20	20	100.00
		pwm_csr_aliasing	4.000s	95.996us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.133m	28.375ms	49	50	98.00
V2	pulse	pwm_rand_output	1.133m	28.375ms	49	50	98.00
V2	blink	pwm_rand_output	1.133m	28.375ms	49	50	98.00
V2	heartbeat	pwm_rand_output	1.133m	28.375ms	49	50	98.00
V2	resolution	pwm_rand_output	1.133m	28.375ms	49	50	98.00
V2	multi_channel	pwm_rand_output	1.133m	28.375ms	49	50	98.00
V2	polarity	pwm_rand_output	1.133m	28.375ms	49	50	98.00
V2	phase	pwm_rand_output	1.133m	28.375ms	49	50	98.00
V2	lowpower	pwm_rand_output	1.133m	28.375ms	49	50	98.00
V2	perf	pwm_perf	55.000s	10.502ms	50	50	100.00
V2	stress_all	pwm_stress_all	5.067m	75.768ms	48	50	96.00
V2	alert_test	pwm_alert_test	17.000s	41.528us	50	50	100.00
V2	intr_test	pwm_intr_test	12.000s	89.765us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	6.000s	315.580us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	6.000s	315.580us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	26.621us	5	5	100.00
		pwm_csr_rw	12.000s	29.718us	20	20	100.00
		pwm_csr_aliasing	4.000s	95.996us	5	5	100.00
		pwm_same_csr_outstanding	3.000s	149.970us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	26.621us	5	5	100.00
		pwm_csr_rw	12.000s	29.718us	20	20	100.00
		pwm_csr_aliasing	4.000s	95.996us	5	5	100.00
		pwm_same_csr_outstanding	3.000s	149.970us	20	20	100.00
V2		TOTAL			287	290	98.97
V2S	tl_intg_err	pwm_tl_intg_err	8.000s	66.888us	20	20	100.00
		pwm_sec_cm	12.000s	39.277us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	8.000s	66.888us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			417	420	99.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.53	99.52	99.14	99.96	95.03	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

5.pwm_stress_all.30754092813036676510331307861265882584901079182879043866575441215636336275241
Line 616, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/5.pwm_stress_all/latest/run.log

  UVM_ERROR @ 39472021479 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [5] did not MATCH
  UVM_INFO @ 39472021479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.pwm_stress_all.33449686514622957827443806563722789436125815975325740715031851759111631871000
Line 117037, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/9.pwm_stress_all/latest/run.log

  UVM_ERROR @ 22964743664 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [4] did not MATCH
  UVM_INFO @ 22964743664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pwm_rand_output has 1 failures.
  - 47.pwm_rand_output.20733560267726614271437310531064309761493691329252283752393904185604545361225
    Line 403, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/47.pwm_rand_output/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```