ROM_CTRL Simulation Results

Wednesday May 24 2023 07:09:34 UTC

GitHub Revision: `26b0ee226`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 844256362

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	36.680s	11.960ms	48	50	96.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.260s	7.626ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.140s	1.969ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.510s	8.374ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	14.240s	8.762ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.450s	4.560ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.140s	1.969ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.240s	8.762ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	10.270s	5.438ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	13.620s	2.069ms	5	5	100.00
V1		TOTAL			113	115	98.26
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	15.570s	2.129ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.935m	20.096ms	45	50	90.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	31.450s	37.943ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	14.510s	9.224ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	18.460s	8.626ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	18.460s	8.626ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.260s	7.626ms	5	5	100.00
		rom_ctrl_csr_rw	15.140s	1.969ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.240s	8.762ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.350s	8.802ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.260s	7.626ms	5	5	100.00
		rom_ctrl_csr_rw	15.140s	1.969ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.240s	8.762ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.350s	8.802ms	20	20	100.00
V2		TOTAL			235	240	97.92
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.460m	69.690ms	48	50	96.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	5.399m	34.686ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.095m	1.743ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.202m	8.862ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.095m	1.743ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.460m	69.690ms	48	50	96.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.460m	69.690ms	48	50	96.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.460m	69.690ms	48	50	96.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.460m	69.690ms	48	50	96.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.460m	69.690ms	48	50	96.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.095m	1.743ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.095m	1.743ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	36.680s	11.960ms	48	50	96.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	36.680s	11.960ms	48	50	96.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	36.680s	11.960ms	48	50	96.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.202m	8.862ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.460m	69.690ms	48	50	96.00
		rom_ctrl_kmac_err_chk	31.450s	37.943ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.460m	69.690ms	48	50	96.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.460m	69.690ms	48	50	96.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.460m	69.690ms	48	50	96.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	5.399m	34.686ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.095m	1.743ms	5	5	100.00
V2S		TOTAL			93	95	97.89
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.790h	209.431ms	35	50	70.00
V3		TOTAL			35	50	70.00
		TOTAL			476	500	95.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.74	97.16	93.12	97.88	86.67	98.68	98.04	98.61

Failure Buckets

UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 12 failures:

Test rom_ctrl_smoke has 2 failures.

4.rom_ctrl_smoke.4170993788
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10020681762 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xa096626f
  UVM_INFO @ 10020681762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.rom_ctrl_smoke.2328207751
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/12.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10011209054 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x11ff6dc4
  UVM_INFO @ 10011209054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_ctrl_stress_all_with_rand_reset has 5 failures.

6.rom_ctrl_stress_all_with_rand_reset.228219801
Line 221, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10007692469 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x16b60cf1
  UVM_INFO @ 10007692469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.rom_ctrl_stress_all_with_rand_reset.3432236026
Line 223, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10128261320 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xf4974c21
  UVM_INFO @ 10128261320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test rom_ctrl_stress_all has 5 failures.

8.rom_ctrl_stress_all.1775406643
Line 221, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/8.rom_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10086905652 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x662c9ef6
  UVM_INFO @ 10086905652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.rom_ctrl_stress_all.3504222201
Line 219, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/12.rom_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10010678813 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x8ed6e5dc
  UVM_INFO @ 10010678813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 10 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 10 failures.
  - 3.rom_ctrl_stress_all_with_rand_reset.4045733783
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:3a57213c-770d-4c7e-acde-2226a1090e4a
```
  - 9.rom_ctrl_stress_all_with_rand_reset.2725129302
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:ff7bdce9-b9e0-4318-85b0-cb36c737772c
```
  - ... and 8 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

Test rom_ctrl_corrupt_sig_fatal_chk has 2 failures.

27.rom_ctrl_corrupt_sig_fatal_chk.474748614
Line 248, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/27.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.rom_ctrl_corrupt_sig_fatal_chk.1299554856
Line 231, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/41.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---