ROM_CTRL Simulation Results

Saturday May 27 2023 07:02:22 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2359737659

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	37.920s	16.808ms	47	50	94.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	13.940s	5.413ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.540s	5.333ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.730s	2.267ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	13.190s	8.329ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	14.150s	8.225ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.540s	5.333ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.190s	8.329ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	13.790s	5.774ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	13.690s	8.866ms	5	5	100.00
V1		TOTAL			112	115	97.39
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	16.010s	2.147ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.396m	9.227ms	46	50	92.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	30.980s	43.086ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	15.060s	9.474ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	18.540s	7.571ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	18.540s	7.571ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	13.940s	5.413ms	5	5	100.00
		rom_ctrl_csr_rw	14.540s	5.333ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.190s	8.329ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.340s	26.456ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	13.940s	5.413ms	5	5	100.00
		rom_ctrl_csr_rw	14.540s	5.333ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.190s	8.329ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.340s	26.456ms	20	20	100.00
V2		TOTAL			236	240	98.33
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.497m	37.490ms	45	50	90.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	5.428m	70.399ms	18	20	90.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.654m	539.549us	5	5	100.00
		rom_ctrl_tl_intg_err	1.190m	2.724ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.654m	539.549us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.497m	37.490ms	45	50	90.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.497m	37.490ms	45	50	90.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.497m	37.490ms	45	50	90.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.497m	37.490ms	45	50	90.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.497m	37.490ms	45	50	90.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.654m	539.549us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.654m	539.549us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	37.920s	16.808ms	47	50	94.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	37.920s	16.808ms	47	50	94.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	37.920s	16.808ms	47	50	94.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.190m	2.724ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.497m	37.490ms	45	50	90.00
		rom_ctrl_kmac_err_chk	30.980s	43.086ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.497m	37.490ms	45	50	90.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.497m	37.490ms	45	50	90.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.497m	37.490ms	45	50	90.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	5.428m	70.399ms	18	20	90.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.654m	539.549us	5	5	100.00
V2S		TOTAL			88	95	92.63
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.240h	81.955ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			467	500	93.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	2	50.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.56	97.16	92.68	97.88	86.67	98.36	98.04	98.14

Failure Buckets

Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 19 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 19 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.2109697421
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:7bf87319-0804-43c9-8f05-b8f2b96a7b5d
```
  - 4.rom_ctrl_stress_all_with_rand_reset.2915308319
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c1ad4ed0-63c0-40a9-8cdb-4039e38051aa
```
  - ... and 17 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 7 failures:

Test rom_ctrl_stress_all has 4 failures.

2.rom_ctrl_stress_all.4266256933
Line 220, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10098064788 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x3de239a
  UVM_INFO @ 10098064788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.rom_ctrl_stress_all.2451575198
Line 221, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/13.rom_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10128800755 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x7471f05c
  UVM_INFO @ 10128800755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test rom_ctrl_smoke has 3 failures.

18.rom_ctrl_smoke.2791553046
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/18.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10010908269 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xe191162d
  UVM_INFO @ 10010908269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.rom_ctrl_smoke.3193860561
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/19.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10018521616 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x9759ec30
  UVM_INFO @ 10018521616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:

Test rom_ctrl_corrupt_sig_fatal_chk has 5 failures.

1.rom_ctrl_corrupt_sig_fatal_chk.445494837
Line 246, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.rom_ctrl_corrupt_sig_fatal_chk.117304444
Line 232, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/11.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 2 failures.

8.rom_ctrl_passthru_mem_tl_intg_err.122689883
Line 219, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/8.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_FATAL @ 10017541485 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xa8370000
  UVM_INFO @ 10017541485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.rom_ctrl_passthru_mem_tl_intg_err.2380319077
Line 219, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/15.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_FATAL @ 10014134142 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xcfef0004
  UVM_INFO @ 10014134142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---