ROM_CTRL Simulation Results

Sunday May 28 2023 07:05:15 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2869101736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	40.390s	17.747ms	44	50	88.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.380s	2.064ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	13.410s	7.651ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	12.970s	19.454ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.410s	10.952ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	14.360s	2.146ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	13.410s	7.651ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.410s	10.952ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	10.880s	1.464ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	14.360s	2.112ms	5	5	100.00
V1		TOTAL			109	115	94.78
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	16.070s	4.373ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.061m	25.594ms	46	50	92.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	30.460s	8.549ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	14.220s	17.766ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	17.380s	4.341ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	17.380s	4.341ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.380s	2.064ms	5	5	100.00
		rom_ctrl_csr_rw	13.410s	7.651ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.410s	10.952ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.300s	13.150ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.380s	2.064ms	5	5	100.00
		rom_ctrl_csr_rw	13.410s	7.651ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.410s	10.952ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.300s	13.150ms	20	20	100.00
V2		TOTAL			235	240	97.92
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	3.855m	29.264ms	49	50	98.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	4.946m	37.722ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.623m	1.374ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.211m	2.370ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.623m	1.374ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.855m	29.264ms	49	50	98.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.855m	29.264ms	49	50	98.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.855m	29.264ms	49	50	98.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.855m	29.264ms	49	50	98.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.855m	29.264ms	49	50	98.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.623m	1.374ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.623m	1.374ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	40.390s	17.747ms	44	50	88.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	40.390s	17.747ms	44	50	88.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	40.390s	17.747ms	44	50	88.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.211m	2.370ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.855m	29.264ms	49	50	98.00
		rom_ctrl_kmac_err_chk	30.460s	8.549ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	3.855m	29.264ms	49	50	98.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.855m	29.264ms	49	50	98.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	3.855m	29.264ms	49	50	98.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	4.946m	37.722ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.623m	1.374ms	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.438h	43.816ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			468	500	93.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	4	66.67
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.67	97.16	93.12	97.88	86.67	98.68	98.04	98.14

Failure Buckets

Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 17 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 17 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.2413065013
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:8544eede-b1a7-4e44-a2e6-253fbda0c13c
```
  - 2.rom_ctrl_stress_all_with_rand_reset.2645667974
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:195715c1-7314-418e-b9f2-276b6bccb52c
```
  - ... and 15 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 13 failures:

Test rom_ctrl_smoke has 6 failures.

1.rom_ctrl_smoke.3280003101
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10021445860 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xe57fce85
  UVM_INFO @ 10021445860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.rom_ctrl_smoke.175115934
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/10.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10007577846 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x61216719
  UVM_INFO @ 10007577846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test rom_ctrl_stress_all has 4 failures.

10.rom_ctrl_stress_all.3831135846
Line 220, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/10.rom_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10089499811 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x4f7f5b3e
  UVM_INFO @ 10089499811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.rom_ctrl_stress_all.1562121741
Line 219, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/24.rom_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10006397310 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x8ee860e0
  UVM_INFO @ 10006397310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test rom_ctrl_stress_all_with_rand_reset has 3 failures.

17.rom_ctrl_stress_all_with_rand_reset.3898741434
Line 221, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10005010205 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x7382934b
  UVM_INFO @ 10005010205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.rom_ctrl_stress_all_with_rand_reset.3496297036
Line 221, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/37.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10008596238 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x96b7d7c3
  UVM_INFO @ 10008596238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_kmac_err_chk has 1 failures.
  - 17.rom_ctrl_kmac_err_chk.1903401400
    Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/17.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 2764161769 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 2764161769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:595) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire has 1 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 34.rom_ctrl_corrupt_sig_fatal_chk.1981272507
    Line 231, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/34.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 1357731605 ps: (cip_base_vseq.sv:595) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
  UVM_INFO @ 1357731605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```