ROM_CTRL Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: `877a77116`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88555427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	42.310s	4.355ms	46	50	92.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	15.390s	2.106ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.510s	8.681ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	11.800s	6.287ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	13.300s	9.838ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	14.160s	2.060ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.510s	8.681ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.300s	9.838ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	12.100s	4.002ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	12.030s	6.778ms	5	5	100.00
V1		TOTAL			111	115	96.52
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	16.000s	2.138ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.231m	6.164ms	46	50	92.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	29.640s	8.395ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	14.030s	2.176ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	17.920s	4.179ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	17.920s	4.179ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	15.390s	2.106ms	5	5	100.00
		rom_ctrl_csr_rw	14.510s	8.681ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.300s	9.838ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.180s	2.169ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	15.390s	2.106ms	5	5	100.00
		rom_ctrl_csr_rw	14.510s	8.681ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.300s	9.838ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.180s	2.169ms	20	20	100.00
V2		TOTAL			236	240	98.33
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.419m	200.000ms	46	50	92.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	4.721m	42.200ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.691m	3.915ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.188m	7.215ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.691m	3.915ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.419m	200.000ms	46	50	92.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.419m	200.000ms	46	50	92.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.419m	200.000ms	46	50	92.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.419m	200.000ms	46	50	92.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.419m	200.000ms	46	50	92.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.691m	3.915ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.691m	3.915ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	42.310s	4.355ms	46	50	92.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	42.310s	4.355ms	46	50	92.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	42.310s	4.355ms	46	50	92.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.188m	7.215ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.419m	200.000ms	46	50	92.00
		rom_ctrl_kmac_err_chk	29.640s	8.395ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.419m	200.000ms	46	50	92.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.419m	200.000ms	46	50	92.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.419m	200.000ms	46	50	92.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	4.721m	42.200ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.691m	3.915ms	5	5	100.00
V2S		TOTAL			91	95	95.79
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.989h	57.420ms	39	50	78.00
V3		TOTAL			39	50	78.00
		TOTAL			477	500	95.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.86	97.16	93.12	97.88	86.67	98.68	98.19	99.30

Failure Buckets

UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 11 failures:

Test rom_ctrl_smoke has 4 failures.

7.rom_ctrl_smoke.3708291813
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/7.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10011801730 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xf3c67190
  UVM_INFO @ 10011801730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.rom_ctrl_smoke.1709154696
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/15.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10016430600 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x46e04b48
  UVM_INFO @ 10016430600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test rom_ctrl_stress_all has 4 failures.

12.rom_ctrl_stress_all.2287313447
Line 219, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/12.rom_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10006706422 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x447dffe5
  UVM_INFO @ 10006706422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.rom_ctrl_stress_all.819785220
Line 220, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/27.rom_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10123618010 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x6e51f690
  UVM_INFO @ 10123618010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test rom_ctrl_stress_all_with_rand_reset has 3 failures.

18.rom_ctrl_stress_all_with_rand_reset.787891300
Line 221, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10019802503 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xb54219e0
  UVM_INFO @ 10019802503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

32.rom_ctrl_stress_all_with_rand_reset.1258444624
Line 221, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/32.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10006792198 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xe2b1f9b1
  UVM_INFO @ 10006792198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.86664260
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:cca93b76-250e-4d83-a443-3a5c9800639b
```
  - 3.rom_ctrl_stress_all_with_rand_reset.3911692588
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:53c867d1-9dd2-4ba1-8d9e-70f12ca70ea2
```
  - ... and 6 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:

Test rom_ctrl_corrupt_sig_fatal_chk has 4 failures.

8.rom_ctrl_corrupt_sig_fatal_chk.1353290119
Line 235, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/8.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.rom_ctrl_corrupt_sig_fatal_chk.339968950
Line 247, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/27.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.