ROM_CTRL/32KB Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: `e9b7e615a7`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	8.990s	1.777ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	10.660s	519.923us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	5.300s	133.048us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.500s	126.823us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	7.850s	516.024us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	8.230s	535.353us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	5.300s	133.048us	20	20	100.00
		rom_ctrl_csr_aliasing	7.850s	516.024us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.100s	250.881us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	4.940s	521.194us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	9.120s	504.802us	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	25.620s	2.285ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	16.820s	1.008ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	7.780s	1.832ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	10.340s	294.587us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	10.340s	294.587us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	10.660s	519.923us	5	5	100.00
		rom_ctrl_csr_rw	5.300s	133.048us	20	20	100.00
		rom_ctrl_csr_aliasing	7.850s	516.024us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.000s	138.800us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	10.660s	519.923us	5	5	100.00
		rom_ctrl_csr_rw	5.300s	133.048us	20	20	100.00
		rom_ctrl_csr_aliasing	7.850s	516.024us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.000s	138.800us	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	3.635m	6.299ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	19.120s	5.034ms	4	20	20.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.722m	404.564us	5	5	100.00
		rom_ctrl_tl_intg_err	1.212m	1.603ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.722m	404.564us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.635m	6.299ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.635m	6.299ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.635m	6.299ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.635m	6.299ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.635m	6.299ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.722m	404.564us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.722m	404.564us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	8.990s	1.777ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	8.990s	1.777ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	8.990s	1.777ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.212m	1.603ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.635m	6.299ms	50	50	100.00
		rom_ctrl_kmac_err_chk	16.820s	1.008ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	3.635m	6.299ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.635m	6.299ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	3.635m	6.299ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	19.120s	5.034ms	4	20	20.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.722m	404.564us	5	5	100.00
V2S		TOTAL			79	95	83.16
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.732h	102.729ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			416	460	90.43

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.28	96.89	92.13	97.67	100.00	98.62	97.30	98.37

Failure Buckets

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_*' while it is being accessed has 15 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 15 failures.

0.rom_ctrl_passthru_mem_tl_intg_err.14554301408159826630992177495977790469249786967910858953024735299345617230729
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 129223960 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 129223960 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 129223960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_ctrl_passthru_mem_tl_intg_err.81007011118210785876749215428306469640778497457265261150879228674578014750989
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 129011322 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 129011322 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 129011322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 13 more failures.

Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 14 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.54597022767604728731802699460209861187285376856116007556923268724242411001218
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:275c04ab-ab92-4121-8467-da03bf0f916f
```
  - 5.rom_ctrl_stress_all_with_rand_reset.76052953417327960951603110521863322175887204373668334081834866754055773992958
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:884820f3-1852-4016-b26f-90c2d9276177
```
  - ... and 12 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.73342195354929029307012339029316269538132733065541866402754495215216272240219
    Line 350, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 108580712475 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 108580712475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.rom_ctrl_stress_all_with_rand_reset.70740321516182422780326172143655126060952223701645514550868304078473652512424
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 216357013 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 216357013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 38.rom_ctrl_stress_all_with_rand_reset.16621958129404064871403258260288086449625278425115538166590770027461785041744
    Line 725, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 311665852999 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 311665852999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.rom_ctrl_stress_all_with_rand_reset.40416609352740882179487978246834671021236874851399836929340117779751859134255
    Line 423, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 231485473096 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 231485473096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.100229796663792915337324735930698673122503849413801885872411071972512731955822
    Line 551, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 60549621790 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 60549621790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.rom_ctrl_stress_all_with_rand_reset.37559392814781256059333441271729446096456876701457584183823287217604048234276
    Line 642, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 42915773546 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 42915773546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_*' while it is being accessed has 1 failures:
- Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 6.rom_ctrl_passthru_mem_tl_intg_err.8904723928878863536216536121850873026076379023983140098657826905449523043113
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_WARNING @ 834255293 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_0' while it is being accessed
  UVM_ERROR @ 834255293 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 834255293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_base_vseq.sv:91) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 43.rom_ctrl_stress_all_with_rand_reset.46706069272790127810362409527294509323969212220352815919115182315153576803901
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/43.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  91831329 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @  91831329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```