ROM_CTRL/32KB Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: `625f353e9c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.360s	137.031us	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	8.160s	135.713us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	5.140s	132.709us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.910s	1.048ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.120s	255.160us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	8.310s	1.069ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	5.140s	132.709us	20	20	100.00
		rom_ctrl_csr_aliasing	5.120s	255.160us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	7.590s	2.049ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	5.120s	128.911us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	8.820s	1.030ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	28.910s	696.315us	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	16.600s	1.983ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	7.970s	591.404us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	10.360s	661.507us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	10.360s	661.507us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	8.160s	135.713us	5	5	100.00
		rom_ctrl_csr_rw	5.140s	132.709us	20	20	100.00
		rom_ctrl_csr_aliasing	5.120s	255.160us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.460s	5.455ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	8.160s	135.713us	5	5	100.00
		rom_ctrl_csr_rw	5.140s	132.709us	20	20	100.00
		rom_ctrl_csr_aliasing	5.120s	255.160us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.460s	5.455ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	3.236m	6.433ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	27.850s	570.806us	6	20	30.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.801m	1.142ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.326m	659.501us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.801m	1.142ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.236m	6.433ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.236m	6.433ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.236m	6.433ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.236m	6.433ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.236m	6.433ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.801m	1.142ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.801m	1.142ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.360s	137.031us	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.360s	137.031us	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.360s	137.031us	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.326m	659.501us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.236m	6.433ms	50	50	100.00
		rom_ctrl_kmac_err_chk	16.600s	1.983ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	3.236m	6.433ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.236m	6.433ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	3.236m	6.433ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	27.850s	570.806us	6	20	30.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.801m	1.142ms	5	5	100.00
V2S		TOTAL			81	95	85.26
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.799h	270.454ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			414	460	90.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.19	96.89	91.85	97.67	100.00	98.28	97.30	98.37

Failure Buckets

Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 17 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 17 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.112304954383522082463876727696044011555923331946709132730019938146943792895028
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:fb01ccb0-93cf-42c4-90f0-feb803b0ff43
```
  - 6.rom_ctrl_stress_all_with_rand_reset.21003795330000628306190117649888276301485395081927790793721295240708450016117
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:207828c7-b9a8-47bc-addc-f59db22a39a3
```
  - ... and 15 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_*' while it is being accessed has 13 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 13 failures.

1.rom_ctrl_passthru_mem_tl_intg_err.32878276973399349817595539307785212868299074325295024475008801208560142441378
Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 6208079783 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 6208079783 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 6208079783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.rom_ctrl_passthru_mem_tl_intg_err.12973689736370640115307519949554919210828783503603516943870090209124291324586
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 172238157 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 172238157 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 172238157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.73451963959476921224018482174700452863532734627642096281443428516464884096011
    Line 1192, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 256444491698 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 256444491698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.rom_ctrl_stress_all_with_rand_reset.67570491551162826787121627581515938386898897365262254757315613364601499957079
    Line 386, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13221338560 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 13221338560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 4 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.109566116872549439685537667453396723389951206511938460036440311897216495659722
    Line 402, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28257885371 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 28257885371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.rom_ctrl_stress_all_with_rand_reset.100771288102145827035914681087200376544272865479634239887278431562457095581892
    Line 381, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25619360892 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 25619360892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 4 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 4 failures.
  - 17.rom_ctrl_stress_all_with_rand_reset.9430242634295921334790317644897388661816655299604729616914247174088970615701
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 760966652 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 760966652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.rom_ctrl_stress_all_with_rand_reset.115287920274319156907793010777902642814140866926016634525954989274506496621852
    Line 385, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 37182764790 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 37182764790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:91) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 31.rom_ctrl_stress_all_with_rand_reset.94757738508790293293114467078246095510003337772208684058609739327453275227412
    Line 270, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 560267353 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 560267353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.rom_ctrl_stress_all_with_rand_reset.36411711247930901363231872234010353411731010390447815118890851950305971829271
    Line 521, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/47.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 77439149787 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 77439149787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_*' while it is being accessed has 1 failures:
- Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 3.rom_ctrl_passthru_mem_tl_intg_err.20676219681449266536303811577282765586873262169862603422601299660051000372399
    Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_WARNING @ 175056395 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_0' while it is being accessed
  UVM_ERROR @ 175056395 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 175056395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```