c8985d6745| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 8.740s | 519.908us | 10 | 10 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 8.170s | 130.117us | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 7.640s | 8.173ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 5.720s | 654.157us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 5.070s | 132.198us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 8.360s | 533.005us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 7.640s | 8.173ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 5.070s | 132.198us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 5.030s | 2.487ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 5.180s | 502.521us | 5 | 5 | 100.00 |
| V1 | TOTAL | 75 | 75 | 100.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 8.940s | 1.943ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 37.380s | 4.084ms | 50 | 50 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 11.590s | 1.651ms | 50 | 50 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 7.930s | 2.048ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 11.390s | 505.876us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 11.390s | 505.876us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 8.170s | 130.117us | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 7.640s | 8.173ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 5.070s | 132.198us | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 9.080s | 1.033ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 8.170s | 130.117us | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 7.640s | 8.173ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 5.070s | 132.198us | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 9.080s | 1.033ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 3.629m | 4.162ms | 49 | 50 | 98.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 28.140s | 543.280us | 3 | 20 | 15.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 1.688m | 280.151us | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 1.191m | 359.586us | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 1.688m | 280.151us | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.629m | 4.162ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.629m | 4.162ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 3.629m | 4.162ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.629m | 4.162ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.629m | 4.162ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 1.688m | 280.151us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 1.688m | 280.151us | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 8.740s | 519.908us | 10 | 10 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 8.740s | 519.908us | 10 | 10 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 8.740s | 519.908us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 1.191m | 359.586us | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 3.629m | 4.162ms | 49 | 50 | 98.00 |
| rom_ctrl_kmac_err_chk | 11.590s | 1.651ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 3.629m | 4.162ms | 49 | 50 | 98.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.629m | 4.162ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 3.629m | 4.162ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 28.140s | 543.280us | 3 | 20 | 15.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 1.688m | 280.151us | 5 | 5 | 100.00 |
| V2S | TOTAL | 77 | 95 | 81.05 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.611h | 78.645ms | 23 | 50 | 46.00 |
| V3 | TOTAL | 23 | 50 | 46.00 | |||
| TOTAL | 415 | 460 | 90.22 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 4 | 4 | 2 | 50.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.19 | 96.89 | 91.85 | 97.67 | 100.00 | 98.28 | 97.30 | 98.37 |
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 16 failures:
4.rom_ctrl_stress_all_with_rand_reset.90344845194517117136817924117704637995723895645084592594024482561340748256585
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:07547462-3e25-4706-9d35-ab08b0186d88
5.rom_ctrl_stress_all_with_rand_reset.36650002535080766513268622404407557797864016781883426398226384218151684663867
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:ab63df89-271a-421a-88f4-511412d43a6f
... and 14 more failures.
UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_*' while it is being accessed has 12 failures:
4.rom_ctrl_passthru_mem_tl_intg_err.84462596532268473006219378591831560513491845446892707816239176248917785976088
Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
UVM_WARNING @ 264696337 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
UVM_ERROR @ 264696337 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
UVM_INFO @ 264696337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.rom_ctrl_passthru_mem_tl_intg_err.6354481469728846489492520038046553335795446553646266186263933189415523262809
Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
UVM_WARNING @ 2843176278 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
UVM_ERROR @ 2843176278 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
UVM_INFO @ 2843176278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_*' while it is being accessed has 5 failures:
0.rom_ctrl_passthru_mem_tl_intg_err.88794436510298119407032604655849504634191440877289321328956719060023759944708
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
UVM_WARNING @ 562616219 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_1' while it is being accessed
UVM_ERROR @ 562616219 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
UVM_INFO @ 562616219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_ctrl_passthru_mem_tl_intg_err.37886187272954062421007473036919459648645096794129973254637078225895354840714
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
UVM_WARNING @ 1385652873 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_1' while it is being accessed
UVM_ERROR @ 1385652873 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
UVM_INFO @ 1385652873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
0.rom_ctrl_stress_all_with_rand_reset.8446265607104919027081027752106690946496662913196352891033167632450533679995
Line 298, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5200385233 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5200385233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.rom_ctrl_stress_all_with_rand_reset.13921434203767541949843137524321023707667636024450900812071790739473909280986
Line 398, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/24.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 23500781815 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 23500781815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 3 failures:
9.rom_ctrl_stress_all_with_rand_reset.45763045841506388962411559877494441724634123742978873631319999411776670324650
Line 293, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 12626721582 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 12626721582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.rom_ctrl_stress_all_with_rand_reset.39362879919521325887568725443067233469018581605861711981284169060330320339943
Line 498, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/26.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 76980969667 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 76980969667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:91) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 3 failures:
19.rom_ctrl_stress_all_with_rand_reset.37865284604086391427994085812673978079107389968319545560743072561421175515165
Line 766, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 56601904065 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
UVM_INFO @ 56601904065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.rom_ctrl_stress_all_with_rand_reset.49310533749888273137403720036695221734295230611775197474021805120213024583146
Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 390554063 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
UVM_INFO @ 390554063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:247) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
6.rom_ctrl_corrupt_sig_fatal_chk.5652107971487665132612680247226732510961905016911078079452732633429819765634
Line 274, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 15407533304 ps: (rom_ctrl_scoreboard.sv:247) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 15407533304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 1 failures:
38.rom_ctrl_stress_all_with_rand_reset.29640428956373072859390116898341254440679636124995082696620722127359278047578
Line 340, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 14560538300 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
UVM_INFO @ 14560538300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---