ROM_CTRL/32KB Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	8.540s	2.079ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	6.860s	511.952us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	5.180s	329.467us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.820s	1.958ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.150s	129.018us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.490s	302.048us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	5.180s	329.467us	20	20	100.00
		rom_ctrl_csr_aliasing	5.150s	129.018us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.030s	1.552ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	4.990s	255.092us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	9.120s	1.024ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	25.500s	8.465ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	16.360s	6.603ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	5.410s	131.167us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	9.910s	154.040us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	9.910s	154.040us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	6.860s	511.952us	5	5	100.00
		rom_ctrl_csr_rw	5.180s	329.467us	20	20	100.00
		rom_ctrl_csr_aliasing	5.150s	129.018us	5	5	100.00
		rom_ctrl_same_csr_outstanding	9.120s	533.064us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	6.860s	511.952us	5	5	100.00
		rom_ctrl_csr_rw	5.180s	329.467us	20	20	100.00
		rom_ctrl_csr_aliasing	5.150s	129.018us	5	5	100.00
		rom_ctrl_same_csr_outstanding	9.120s	533.064us	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	3.181m	38.647ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	27.130s	1.100ms	7	20	35.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.723m	322.633us	5	5	100.00
		rom_ctrl_tl_intg_err	1.176m	1.061ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.723m	322.633us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.181m	38.647ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.181m	38.647ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.181m	38.647ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.181m	38.647ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.181m	38.647ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.723m	322.633us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.723m	322.633us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	8.540s	2.079ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	8.540s	2.079ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	8.540s	2.079ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.176m	1.061ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.181m	38.647ms	50	50	100.00
		rom_ctrl_kmac_err_chk	16.360s	6.603ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	3.181m	38.647ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.181m	38.647ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	3.181m	38.647ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	27.130s	1.100ms	7	20	35.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.723m	322.633us	5	5	100.00
V2S		TOTAL			82	95	86.32
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.436h	23.896ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			418	460	90.87

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.22	96.89	91.85	97.67	100.00	98.28	97.45	98.37

Failure Buckets

Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 16 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 16 failures.
  - 12.rom_ctrl_stress_all_with_rand_reset.15691200563292555959218238314389869456180981552732261385845308358466016728327
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:ce363aa2-4a47-41d9-a23f-798cde7c88bb
```
  - 14.rom_ctrl_stress_all_with_rand_reset.39371776507073178129499289642356762125865440867850600860782711649681927946841
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c7e65121-9425-4c6c-88ef-ae09b3d6dcde
```
  - ... and 14 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_*' while it is being accessed has 8 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 8 failures.

1.rom_ctrl_passthru_mem_tl_intg_err.103615961465997842105264876270295922712992224461442765811760676967233777396921
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 461287716 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 461287716 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 461287716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.rom_ctrl_passthru_mem_tl_intg_err.47356177603888126615292220390378827070002439948528870967271414935983620717350
Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 2894602394 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 2894602394 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 2894602394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.42878915124370009421671007606620769999232292540455625755555867275456900726253
    Line 270, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2863837235 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 2863837235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.rom_ctrl_stress_all_with_rand_reset.99291364746629287667253394253368074839103103883506003793329441252068369508218
    Line 350, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 16746702957 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 16746702957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_*' while it is being accessed has 5 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 5 failures.

0.rom_ctrl_passthru_mem_tl_intg_err.91190495573969147486151042690190629003438106743390103076085976952107179068302
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 124269460 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_0' while it is being accessed
  UVM_ERROR @ 124269460 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 124269460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.rom_ctrl_passthru_mem_tl_intg_err.44482735830126194571547067439344467472939815001693309726999004878153089215807
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 825231684 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_0' while it is being accessed
  UVM_ERROR @ 825231684 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 825231684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 4 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.85500313670160938348766030998542832933430699138744217775121826879912710271246
    Line 418, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10664901915 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10664901915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.rom_ctrl_stress_all_with_rand_reset.75312558466465218408321275320936367105195469096638813389919011661337469241780
    Line 274, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/25.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1048475877 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1048475877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:91) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.37096993376200595392992196776040058677460108556010343067042455664893935342446
    Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 264094657 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 264094657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.rom_ctrl_stress_all_with_rand_reset.21930313422797080824356808526684425103773562738589075017942242592654157686743
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/39.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  86571718 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @  86571718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 17.rom_ctrl_stress_all_with_rand_reset.92828837711898967276471371275364867871568936800017973725308300172599619427120
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  90181136 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @  90181136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```