0825c81be0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 8.340s | 1.022ms | 10 | 10 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 7.270s | 277.495us | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 4.540s | 133.912us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 4.580s | 260.319us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 4.420s | 1.132ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 6.080s | 151.425us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 4.540s | 133.912us | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 4.420s | 1.132ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 4.370s | 496.658us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 4.460s | 132.572us | 5 | 5 | 100.00 |
| V1 | TOTAL | 75 | 75 | 100.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 7.670s | 514.697us | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 23.680s | 6.082ms | 50 | 50 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 13.800s | 5.482ms | 49 | 50 | 98.00 |
| V2 | alert_test | rom_ctrl_alert_test | 6.510s | 520.853us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 9.090s | 167.734us | 19 | 20 | 95.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 9.090s | 167.734us | 19 | 20 | 95.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 7.270s | 277.495us | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 4.540s | 133.912us | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 4.420s | 1.132ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 6.150s | 966.312us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 7.270s | 277.495us | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 4.540s | 133.912us | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 4.420s | 1.132ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 6.150s | 966.312us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 238 | 240 | 99.17 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 3.318m | 22.649ms | 50 | 50 | 100.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 37.290s | 12.480ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 1.736m | 721.182us | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 1.118m | 279.316us | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 1.736m | 721.182us | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.318m | 22.649ms | 50 | 50 | 100.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.318m | 22.649ms | 50 | 50 | 100.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 3.318m | 22.649ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.318m | 22.649ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.318m | 22.649ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 1.736m | 721.182us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 1.736m | 721.182us | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 8.340s | 1.022ms | 10 | 10 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 8.340s | 1.022ms | 10 | 10 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 8.340s | 1.022ms | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 1.118m | 279.316us | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 3.318m | 22.649ms | 50 | 50 | 100.00 |
| rom_ctrl_kmac_err_chk | 13.800s | 5.482ms | 49 | 50 | 98.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 3.318m | 22.649ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.318m | 22.649ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 3.318m | 22.649ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 37.290s | 12.480ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 1.736m | 721.182us | 5 | 5 | 100.00 |
| V2S | TOTAL | 95 | 95 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 4.750m | 9.660ms | 46 | 50 | 92.00 |
| V3 | TOTAL | 46 | 50 | 92.00 | |||
| TOTAL | 454 | 460 | 98.70 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 4 | 66.67 |
| V2S | 4 | 4 | 4 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.49 | 96.89 | 92.13 | 97.67 | 100.00 | 98.62 | 98.05 | 99.06 |
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 4 failures:
13.rom_ctrl_stress_all_with_rand_reset.93995834522625265642182870623984364611880808304720909820118083322930795242559
Line 101, in log /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 2734845338 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 2734845338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.rom_ctrl_stress_all_with_rand_reset.52420965247146816261709253137832443714233844273268280721117538575671934879950
Line 97, in log /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 3801525229 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 3801525229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:254) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:
Test rom_ctrl_tl_errors has 1 failures.
14.rom_ctrl_tl_errors.94696832914627805802686650345815054883047123988280627673182937630434469677807
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_tl_errors/latest/run.log
UVM_ERROR @ 1659482468 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 1659482468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_ctrl_kmac_err_chk has 1 failures.
16.rom_ctrl_kmac_err_chk.73269902229601851866223813346934122140762714413676890373186513573959155937717
Line 64, in log /workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_kmac_err_chk/latest/run.log
UVM_ERROR @ 2764679135 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 2764679135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---