ROM_CTRL/32KB Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: `e733a8ef8a`

Branch: os_regression_2024_08_24

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	12.470s	1.051ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	12.990s	131.660us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.460s	523.679us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.690s	500.572us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.650s	127.106us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	11.090s	2.019ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.460s	523.679us	20	20	100.00
		rom_ctrl_csr_aliasing	6.650s	127.106us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	7.120s	136.605us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	7.280s	261.402us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	12.830s	523.710us	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	43.070s	709.748us	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	23.770s	1.030ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	10.870s	525.387us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	16.740s	1.992ms	19	20	95.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	16.740s	1.992ms	19	20	95.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	12.990s	131.660us	5	5	100.00
		rom_ctrl_csr_rw	7.460s	523.679us	20	20	100.00
		rom_ctrl_csr_aliasing	6.650s	127.106us	5	5	100.00
		rom_ctrl_same_csr_outstanding	11.570s	2.137ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	12.990s	131.660us	5	5	100.00
		rom_ctrl_csr_rw	7.460s	523.679us	20	20	100.00
		rom_ctrl_csr_aliasing	6.650s	127.106us	5	5	100.00
		rom_ctrl_same_csr_outstanding	11.570s	2.137ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.332m	15.796ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.179m	12.456ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	2.658m	2.508ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.935m	452.560us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	2.658m	2.508ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.332m	15.796ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.332m	15.796ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.332m	15.796ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.332m	15.796ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.332m	15.796ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	2.658m	2.508ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	2.658m	2.508ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	12.470s	1.051ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	12.470s	1.051ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	12.470s	1.051ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.935m	452.560us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.332m	15.796ms	50	50	100.00
		rom_ctrl_kmac_err_chk	23.770s	1.030ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.332m	15.796ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.332m	15.796ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.332m	15.796ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.179m	12.456ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	2.658m	2.508ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	6.606m	16.917ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			457	460	99.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.42	96.89	91.99	97.67	100.00	98.28	98.05	99.06

Failure Buckets

UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 18.rom_ctrl_stress_all_with_rand_reset.24879064653538299504934550155766657874608854182794226818362436223811277042609
    Line 165, in log /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 6186993229 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 6186993229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.rom_ctrl_stress_all_with_rand_reset.76339928437913550608010525672865181244283200306554561113854671123119541766908
    Line 199, in log /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 16916507231 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 16916507231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:254) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_tl_errors has 1 failures.
  - 11.rom_ctrl_tl_errors.3999924015760843404226184440774900804887487871847279034947010187609290466106
    Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_24/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_tl_errors/latest/run.log
```
  UVM_ERROR @ 1659377981 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 1659377981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: e733a8ef8a

Branch: os_regression_2024_08_24

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e733a8ef8a`