ROM_CTRL/32KB Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: 4674f625b3

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 13.130s 533.638us 10 10 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 10.340s 129.818us 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 7.220s 132.931us 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.940s 1.002ms 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.640s 500.145us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 10.850s 3.568ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.220s 132.931us 20 20 100.00
rom_ctrl_csr_aliasing 7.640s 500.145us 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 7.080s 131.421us 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.840s 379.397us 5 5 100.00
V1 TOTAL 75 75 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 12.810s 2.384ms 50 50 100.00
V2 stress_all rom_ctrl_stress_all 28.940s 446.823us 50 50 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 23.700s 4.455ms 50 50 100.00
V2 alert_test rom_ctrl_alert_test 10.750s 503.703us 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 12.420s 538.919us 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 12.420s 538.919us 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 10.340s 129.818us 5 5 100.00
rom_ctrl_csr_rw 7.220s 132.931us 20 20 100.00
rom_ctrl_csr_aliasing 7.640s 500.145us 5 5 100.00
rom_ctrl_same_csr_outstanding 11.570s 2.070ms 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 10.340s 129.818us 5 5 100.00
rom_ctrl_csr_rw 7.220s 132.931us 20 20 100.00
rom_ctrl_csr_aliasing 7.640s 500.145us 5 5 100.00
rom_ctrl_same_csr_outstanding 11.570s 2.070ms 20 20 100.00
V2 TOTAL 240 240 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 3.614m 11.966ms 50 50 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 39.180s 2.221ms 20 20 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.306m 1.162ms 5 5 100.00
rom_ctrl_tl_intg_err 1.444m 450.002us 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.306m 1.162ms 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 3.614m 11.966ms 50 50 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 3.614m 11.966ms 50 50 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 3.614m 11.966ms 50 50 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 3.614m 11.966ms 50 50 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 3.614m 11.966ms 50 50 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.306m 1.162ms 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.306m 1.162ms 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 13.130s 533.638us 10 10 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 13.130s 533.638us 10 10 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 13.130s 533.638us 10 10 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.444m 450.002us 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 3.614m 11.966ms 50 50 100.00
rom_ctrl_kmac_err_chk 23.700s 4.455ms 50 50 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 3.614m 11.966ms 50 50 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 3.614m 11.966ms 50 50 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 3.614m 11.966ms 50 50 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 39.180s 2.221ms 20 20 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.306m 1.162ms 5 5 100.00
V2S TOTAL 95 95 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 6.055m 22.801ms 46 50 92.00
V3 TOTAL 46 50 92.00
TOTAL 456 460 99.13

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.43 96.89 91.99 97.67 100.00 98.28 97.90 99.30

Failure Buckets

Past Results