ROM_CTRL/32KB Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: `a861deb3de`

Branch: os_regression_2024_08_28

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	10.250s	2.043ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	11.700s	134.617us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	9.620s	2.058ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.330s	497.224us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	7.140s	251.237us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	8.710s	925.593us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	9.620s	2.058ms	20	20	100.00
		rom_ctrl_csr_aliasing	7.140s	251.237us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	7.150s	496.278us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	7.140s	2.505ms	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	13.280s	2.086ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	49.840s	4.224ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	23.640s	1.010ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	10.920s	495.420us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	14.160s	495.836us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	14.160s	495.836us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	11.700s	134.617us	5	5	100.00
		rom_ctrl_csr_rw	9.620s	2.058ms	20	20	100.00
		rom_ctrl_csr_aliasing	7.140s	251.237us	5	5	100.00
		rom_ctrl_same_csr_outstanding	10.160s	141.762us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	11.700s	134.617us	5	5	100.00
		rom_ctrl_csr_rw	9.620s	2.058ms	20	20	100.00
		rom_ctrl_csr_aliasing	7.140s	251.237us	5	5	100.00
		rom_ctrl_same_csr_outstanding	10.160s	141.762us	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.464m	55.197ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	48.430s	1.607ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	2.503m	947.705us	5	5	100.00
		rom_ctrl_tl_intg_err	1.505m	265.078us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	2.503m	947.705us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.464m	55.197ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.464m	55.197ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.464m	55.197ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.464m	55.197ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.464m	55.197ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	2.503m	947.705us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	2.503m	947.705us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	10.250s	2.043ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	10.250s	2.043ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	10.250s	2.043ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.505m	265.078us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.464m	55.197ms	50	50	100.00
		rom_ctrl_kmac_err_chk	23.640s	1.010ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.464m	55.197ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.464m	55.197ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.464m	55.197ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	48.430s	1.607ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	2.503m	947.705us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	5.845m	18.190ms	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			457	460	99.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.53	96.89	92.42	97.67	100.00	98.62	98.05	99.06

Failure Buckets

UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 3.rom_ctrl_stress_all_with_rand_reset.40657608645986444290087662671746253512612745850191299543399414248777799430139
    Line 143, in log /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2454614802 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 2454614802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.rom_ctrl_stress_all_with_rand_reset.109296085204582016752320771386642627175002760402852802320863356145328488661292
    Line 137, in log /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11953846905 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 11953846905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:254) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 27.rom_ctrl_stress_all_with_rand_reset.26936484362498210744454975798215607363457740823387185197168612468706181145430
    Line 129, in log /workspaces/repo/scratch/os_regression_2024_08_28/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 45149800296 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 45149800296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: a861deb3de

Branch: os_regression_2024_08_28

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `a861deb3de`