ROM_CTRL/32KB Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: ed1c41cd0f

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 9.430s 535.460us 10 10 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 14.810s 949.323us 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 7.650s 521.728us 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.840s 567.131us 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.520s 638.362us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 10.030s 511.593us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.650s 521.728us 20 20 100.00
rom_ctrl_csr_aliasing 6.520s 638.362us 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 10.640s 974.205us 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.090s 178.055us 5 5 100.00
V1 TOTAL 75 75 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 12.380s 527.848us 50 50 100.00
V2 stress_all rom_ctrl_stress_all 31.610s 735.338us 50 50 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 23.520s 988.110us 50 50 100.00
V2 alert_test rom_ctrl_alert_test 11.130s 508.460us 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 14.910s 378.763us 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 14.910s 378.763us 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 14.810s 949.323us 5 5 100.00
rom_ctrl_csr_rw 7.650s 521.728us 20 20 100.00
rom_ctrl_csr_aliasing 6.520s 638.362us 5 5 100.00
rom_ctrl_same_csr_outstanding 9.210s 384.334us 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 14.810s 949.323us 5 5 100.00
rom_ctrl_csr_rw 7.650s 521.728us 20 20 100.00
rom_ctrl_csr_aliasing 6.520s 638.362us 5 5 100.00
rom_ctrl_same_csr_outstanding 9.210s 384.334us 20 20 100.00
V2 TOTAL 240 240 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 3.996m 46.879ms 50 50 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 41.620s 819.881us 20 20 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.775m 343.089us 5 5 100.00
rom_ctrl_tl_intg_err 1.560m 220.804us 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.775m 343.089us 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 3.996m 46.879ms 50 50 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 3.996m 46.879ms 50 50 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 3.996m 46.879ms 50 50 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 3.996m 46.879ms 50 50 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 3.996m 46.879ms 50 50 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.775m 343.089us 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.775m 343.089us 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 9.430s 535.460us 10 10 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 9.430s 535.460us 10 10 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 9.430s 535.460us 10 10 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.560m 220.804us 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 3.996m 46.879ms 50 50 100.00
rom_ctrl_kmac_err_chk 23.520s 988.110us 50 50 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 3.996m 46.879ms 50 50 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 3.996m 46.879ms 50 50 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 3.996m 46.879ms 50 50 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 41.620s 819.881us 20 20 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.775m 343.089us 5 5 100.00
V2S TOTAL 95 95 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 7.953m 23.637ms 47 50 94.00
V3 TOTAL 47 50 94.00
TOTAL 457 460 99.35

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.60 96.89 92.56 97.67 100.00 98.97 98.05 99.06

Failure Buckets

Past Results