ROM_CTRL/32KB Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: 372a6306e0

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 10.110s 277.735us 10 10 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 7.620s 89.929us 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 7.770s 501.090us 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.620s 250.717us 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.760s 128.453us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 8.210s 2.619ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.770s 501.090us 20 20 100.00
rom_ctrl_csr_aliasing 4.760s 128.453us 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 6.280s 86.460us 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.020s 778.762us 5 5 100.00
V1 TOTAL 75 75 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 13.650s 504.863us 50 50 100.00
V2 stress_all rom_ctrl_stress_all 38.540s 2.027ms 50 50 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 17.580s 261.105us 50 50 100.00
V2 alert_test rom_ctrl_alert_test 10.250s 495.763us 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 12.370s 1.824ms 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 12.370s 1.824ms 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 7.620s 89.929us 5 5 100.00
rom_ctrl_csr_rw 7.770s 501.090us 20 20 100.00
rom_ctrl_csr_aliasing 4.760s 128.453us 5 5 100.00
rom_ctrl_same_csr_outstanding 9.990s 612.338us 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 7.620s 89.929us 5 5 100.00
rom_ctrl_csr_rw 7.770s 501.090us 20 20 100.00
rom_ctrl_csr_aliasing 4.760s 128.453us 5 5 100.00
rom_ctrl_same_csr_outstanding 9.990s 612.338us 20 20 100.00
V2 TOTAL 240 240 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 4.124m 14.626ms 50 50 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 35.160s 859.312us 20 20 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.278m 372.603us 5 5 100.00
rom_ctrl_tl_intg_err 1.480m 502.749us 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.278m 372.603us 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 4.124m 14.626ms 50 50 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 4.124m 14.626ms 50 50 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 4.124m 14.626ms 50 50 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 4.124m 14.626ms 50 50 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 4.124m 14.626ms 50 50 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.278m 372.603us 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.278m 372.603us 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 10.110s 277.735us 10 10 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 10.110s 277.735us 10 10 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 10.110s 277.735us 10 10 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.480m 502.749us 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 4.124m 14.626ms 50 50 100.00
rom_ctrl_kmac_err_chk 17.580s 261.105us 50 50 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 4.124m 14.626ms 50 50 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 4.124m 14.626ms 50 50 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 4.124m 14.626ms 50 50 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 35.160s 859.312us 20 20 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.278m 372.603us 5 5 100.00
V2S TOTAL 95 95 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 6.148m 31.852ms 46 50 92.00
V3 TOTAL 46 50 92.00
TOTAL 456 460 99.13

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.65 96.89 92.56 97.67 100.00 98.62 98.05 99.77

Failure Buckets

Past Results