ROM_CTRL/32KB Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: af2d1709f9

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 9.350s 785.661us 10 10 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 12.510s 284.395us 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 7.430s 251.633us 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.790s 490.380us 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.440s 126.817us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 8.030s 269.788us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.430s 251.633us 20 20 100.00
rom_ctrl_csr_aliasing 7.440s 126.817us 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 7.290s 347.036us 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 10.080s 521.072us 5 5 100.00
V1 TOTAL 75 75 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 11.750s 2.098ms 50 50 100.00
V2 stress_all rom_ctrl_stress_all 32.570s 552.402us 50 50 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 17.080s 520.224us 50 50 100.00
V2 alert_test rom_ctrl_alert_test 10.940s 515.842us 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 12.890s 143.554us 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 12.890s 143.554us 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 12.510s 284.395us 5 5 100.00
rom_ctrl_csr_rw 7.430s 251.633us 20 20 100.00
rom_ctrl_csr_aliasing 7.440s 126.817us 5 5 100.00
rom_ctrl_same_csr_outstanding 10.320s 137.766us 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 12.510s 284.395us 5 5 100.00
rom_ctrl_csr_rw 7.430s 251.633us 20 20 100.00
rom_ctrl_csr_aliasing 7.440s 126.817us 5 5 100.00
rom_ctrl_same_csr_outstanding 10.320s 137.766us 20 20 100.00
V2 TOTAL 240 240 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 3.258m 8.898ms 50 50 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 40.750s 3.263ms 20 20 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.282m 2.353ms 5 5 100.00
rom_ctrl_tl_intg_err 1.384m 448.751us 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.282m 2.353ms 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 3.258m 8.898ms 50 50 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 3.258m 8.898ms 50 50 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 3.258m 8.898ms 50 50 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 3.258m 8.898ms 50 50 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 3.258m 8.898ms 50 50 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.282m 2.353ms 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.282m 2.353ms 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 9.350s 785.661us 10 10 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 9.350s 785.661us 10 10 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 9.350s 785.661us 10 10 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.384m 448.751us 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 3.258m 8.898ms 50 50 100.00
rom_ctrl_kmac_err_chk 17.080s 520.224us 50 50 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 3.258m 8.898ms 50 50 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 3.258m 8.898ms 50 50 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 3.258m 8.898ms 50 50 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 40.750s 3.263ms 20 20 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.282m 2.353ms 5 5 100.00
V2S TOTAL 95 95 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 6.816m 5.607ms 45 50 90.00
V3 TOTAL 45 50 90.00
TOTAL 455 460 98.91

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.51 96.89 92.28 97.67 100.00 98.62 98.05 99.06

Failure Buckets

Past Results