ROM_CTRL/64KB Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: `be3d980075`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.323m	13.587ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	29.030s	4.524ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	35.210s	4.285ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	28.830s	6.736ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	29.390s	3.836ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	35.140s	9.721ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	35.210s	4.285ms	20	20	100.00
		rom_ctrl_csr_aliasing	29.390s	3.836ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	33.990s	8.785ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	22.210s	2.483ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	34.360s	8.223ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	4.986m	29.861ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.177m	33.931ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	33.330s	22.351ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	36.500s	34.899ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	36.500s	34.899ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	29.030s	4.524ms	5	5	100.00
		rom_ctrl_csr_rw	35.210s	4.285ms	20	20	100.00
		rom_ctrl_csr_aliasing	29.390s	3.836ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	37.420s	4.604ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	29.030s	4.524ms	5	5	100.00
		rom_ctrl_csr_rw	35.210s	4.285ms	20	20	100.00
		rom_ctrl_csr_aliasing	29.390s	3.836ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	37.420s	4.604ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	15.293m	87.601ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.106m	84.842ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.079m	29.145ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.684m	1.683ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.079m	29.145ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.293m	87.601ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.293m	87.601ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	15.293m	87.601ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.293m	87.601ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.293m	87.601ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.079m	29.145ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.079m	29.145ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.323m	13.587ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.323m	13.587ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.323m	13.587ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.684m	1.683ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	15.293m	87.601ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.177m	33.931ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	15.293m	87.601ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.293m	87.601ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	15.293m	87.601ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.106m	84.842ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.079m	29.145ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.705h	82.999ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			463	500	92.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	4	66.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.73	96.97	93.44	97.88	100.00	98.69	98.03	99.07

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 28 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.37206511910508156084239578195194756743153151255728534532102694705563498234267
    Line 442, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28335081385 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 28335081385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.rom_ctrl_stress_all_with_rand_reset.110294082351041439853784518424735135179852110738617405215261122692571123565172
    Line 339, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 35955357365 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 35955357365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 4 failures.
  - 3.rom_ctrl_stress_all_with_rand_reset.19024940382657471495688974497359504907069655996075221125826991174181899175090
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:62eeb50a-7542-46cd-9a72-5e07d32e9964
```
  - 25.rom_ctrl_stress_all_with_rand_reset.13606872347687962116272204606402491202826604814069431681287736686192872628226
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:001172fa-7101-4877-96fa-194b02b4e604
```
  - ... and 2 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.10876022280279392797252994166743636909202874195166368774029533687558299049199
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11259973500 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xa92213f9
  UVM_INFO @ 11259973500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.rom_ctrl_stress_all_with_rand_reset.94032388165264030552059065278112208928652833054802733994361800618759853200006
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10886747299 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x2a7b0cd7
  UVM_INFO @ 10886747299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_kmac_err_chk has 1 failures.
  - 45.rom_ctrl_kmac_err_chk.81083432497622281942460136229655498452736277123866061754288041881668637549649
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 6593111167 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 6593111167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all has 1 failures.
  - 49.rom_ctrl_stress_all.22039457150735785037866040000629271658914695560479463675182414350415425347447
    Line 253, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40112277963 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x8d5a635e
  UVM_INFO @ 40112277963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: be3d980075

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `be3d980075`