ROM_CTRL/64KB Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: `c42c47ec2d`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.610m	8.622ms	47	50	94.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	34.260s	3.589ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	33.840s	8.916ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	28.630s	3.580ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	29.870s	3.508ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	34.780s	35.603ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	33.840s	8.916ms	20	20	100.00
		rom_ctrl_csr_aliasing	29.870s	3.508ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	32.040s	16.256ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	31.110s	3.766ms	5	5	100.00
V1		TOTAL			112	115	97.39
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	34.790s	3.960ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	4.343m	32.778ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.194m	8.772ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	33.100s	4.426ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	35.790s	7.382ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	35.790s	7.382ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	34.260s	3.589ms	5	5	100.00
		rom_ctrl_csr_rw	33.840s	8.916ms	20	20	100.00
		rom_ctrl_csr_aliasing	29.870s	3.508ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	32.550s	8.510ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	34.260s	3.589ms	5	5	100.00
		rom_ctrl_csr_rw	33.840s	8.916ms	20	20	100.00
		rom_ctrl_csr_aliasing	29.870s	3.508ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	32.550s	8.510ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	17.816m	409.069ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.260m	26.106ms	19	20	95.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.202m	14.842ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.904m	16.864ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.202m	14.842ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	17.816m	409.069ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	17.816m	409.069ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	17.816m	409.069ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	17.816m	409.069ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	17.816m	409.069ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.202m	14.842ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.202m	14.842ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.610m	8.622ms	47	50	94.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.610m	8.622ms	47	50	94.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.610m	8.622ms	47	50	94.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.904m	16.864ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	17.816m	409.069ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.194m	8.772ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	17.816m	409.069ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	17.816m	409.069ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	17.816m	409.069ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.260m	26.106ms	19	20	95.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.202m	14.842ms	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.918h	55.989ms	6	50	12.00
V3		TOTAL			6	50	12.00
		TOTAL			452	500	90.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.21	96.89	91.99	97.68	100.00	98.28	97.30	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 29 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.89257052949214473583111822119490444406119009673859830346189699023380471574343
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2132568409 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2132568409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rom_ctrl_stress_all_with_rand_reset.77231375969528097471766801702935872187901107661948809877506087397419888500358
    Line 265, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1231139119 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1231139119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.103546502288216020399963131382642092977077559803660999908438401572153486252120
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:6d026fcd-4548-4922-a641-69f64e3e6108
```
  - 8.rom_ctrl_stress_all_with_rand_reset.99520991297189679455521550985494759046458328347226194299826643913868313363823
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:fc0780b1-d1bd-41d4-938b-580c2f214121
```
  - ... and 6 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.94629004209552583900774940859701051882437271417717190878484979431914857451538
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10529689319 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x1a6f03fd
  UVM_INFO @ 10529689319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.rom_ctrl_stress_all_with_rand_reset.103525663799168176484794064925769083941231752277191688527078998673554176881084
    Line 291, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 25695545422 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x44a80a05
  UVM_INFO @ 25695545422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test rom_ctrl_smoke has 3 failures.
  - 2.rom_ctrl_smoke.18255938073536558817680764651980850758556180901605937763479664960887760379714
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40009083713 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x1674022
  UVM_INFO @ 40009083713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.rom_ctrl_smoke.39998560242297025068609741450155781365142754557569916875543777110923003904315
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40007885017 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x47699883
  UVM_INFO @ 40007885017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 19.rom_ctrl_passthru_mem_tl_intg_err.6403648654190771122585891414218486740491388538584765096801357541456398081857
    Line 263, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: c42c47ec2d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c42c47ec2d`