ROM_CTRL/64KB Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: `2e5d86c9b5`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.417m	17.071ms	49	50	98.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	30.610s	38.328ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	30.660s	40.034ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	32.090s	4.059ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	33.040s	16.372ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	32.580s	15.748ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	30.660s	40.034ms	20	20	100.00
		rom_ctrl_csr_aliasing	33.040s	16.372ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	29.330s	3.625ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	23.030s	5.270ms	5	5	100.00
V1		TOTAL			114	115	99.13
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	36.390s	71.232ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	4.364m	35.025ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.166m	9.671ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	33.390s	16.337ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	39.420s	4.183ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	39.420s	4.183ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	30.610s	38.328ms	5	5	100.00
		rom_ctrl_csr_rw	30.660s	40.034ms	20	20	100.00
		rom_ctrl_csr_aliasing	33.040s	16.372ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	32.070s	3.587ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	30.610s	38.328ms	5	5	100.00
		rom_ctrl_csr_rw	30.660s	40.034ms	20	20	100.00
		rom_ctrl_csr_aliasing	33.040s	16.372ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	32.070s	3.587ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	19.264m	113.468ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.262m	47.108ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.207m	4.749ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.918m	4.057ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.207m	4.749ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.264m	113.468ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.264m	113.468ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	19.264m	113.468ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.264m	113.468ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.264m	113.468ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.207m	4.749ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.207m	4.749ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.417m	17.071ms	49	50	98.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.417m	17.071ms	49	50	98.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.417m	17.071ms	49	50	98.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.918m	4.057ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	19.264m	113.468ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.166m	9.671ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	19.264m	113.468ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.264m	113.468ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	19.264m	113.468ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.262m	47.108ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.207m	4.749ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.627h	17.292ms	10	50	20.00
V3		TOTAL			10	50	20.00
		TOTAL			459	500	91.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.19	96.89	91.85	97.68	100.00	98.28	97.30	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 27 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.1719224577254212651121094283352728974991838059536310316103284109209886182104
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 109580514 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 109580514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.rom_ctrl_stress_all_with_rand_reset.77930461372629182183351534361481880727843971047331881531991964500868908436483
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3962558250 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3962558250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 10 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 10 failures.
  - 13.rom_ctrl_stress_all_with_rand_reset.10808049024715402368361564644543734710923953070247321465302924201519983367052
    Line 303, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 37761930323 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x5f7946de
  UVM_INFO @ 37761930323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.rom_ctrl_stress_all_with_rand_reset.26514798274775160147673617344075328502865130648406100254560431061897491244944
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10005639027 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xaa0e8ba9
  UVM_INFO @ 10005639027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 6.rom_ctrl_stress_all_with_rand_reset.85629437280143772307704211380508635078586311083452840780747730304518064946690
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:79e56f5c-c54a-4bb8-a531-58e54296fa85
```
  - 24.rom_ctrl_stress_all_with_rand_reset.81162499727970459853274540282594128134609031215779405457723821133249943789519
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:38199d15-cddb-4444-9473-bbc140f10cc7
```
  - ... and 1 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_smoke has 1 failures.
  - 39.rom_ctrl_smoke.87989162561701189422643286041886082317129512958748723067968833428818643771904
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 79908790581 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x8e4dd5f5
  UVM_INFO @ 79908790581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: 2e5d86c9b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `2e5d86c9b5`