ROM_CTRL/64KB Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: `6a84251492`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.325m	7.547ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	36.920s	8.518ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	32.100s	40.211ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	27.180s	12.721ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	32.940s	8.391ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	33.200s	4.405ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	32.100s	40.211ms	20	20	100.00
		rom_ctrl_csr_aliasing	32.940s	8.391ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	29.450s	3.693ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	25.960s	12.271ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	34.000s	4.237ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	3.222m	23.341ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.219m	93.037ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	33.810s	11.898ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	34.440s	7.798ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	34.440s	7.798ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	36.920s	8.518ms	5	5	100.00
		rom_ctrl_csr_rw	32.100s	40.211ms	20	20	100.00
		rom_ctrl_csr_aliasing	32.940s	8.391ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	38.140s	58.362ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	36.920s	8.518ms	5	5	100.00
		rom_ctrl_csr_rw	32.100s	40.211ms	20	20	100.00
		rom_ctrl_csr_aliasing	32.940s	8.391ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	38.140s	58.362ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	20.387m	527.115ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.106m	86.787ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.851m	3.780ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.990m	8.827ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.851m	3.780ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	20.387m	527.115ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	20.387m	527.115ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	20.387m	527.115ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	20.387m	527.115ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	20.387m	527.115ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.851m	3.780ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.851m	3.780ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.325m	7.547ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.325m	7.547ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.325m	7.547ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.990m	8.827ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	20.387m	527.115ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.219m	93.037ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	20.387m	527.115ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	20.387m	527.115ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	20.387m	527.115ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.106m	86.787ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.851m	3.780ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.432h	34.533ms	6	50	12.00
V3		TOTAL			6	50	12.00
		TOTAL			456	500	91.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.21	96.89	91.99	97.68	100.00	98.28	97.30	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 35 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.78237443901888580171856818145915957011768164168781488209316245991238901491086
    Line 293, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7094927897 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7094927897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.73759108734618636747629482972817052922807160198433029645177655738224818212404
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 225749248 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 225749248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 33 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 6.rom_ctrl_stress_all_with_rand_reset.34157001732612541203354397931235973230323507901441925700287113538279925981185
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10019004476 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x47cf5870
  UVM_INFO @ 10019004476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.rom_ctrl_stress_all_with_rand_reset.90767186465512131604550381055296770514059351033664422157042502069947853936111
    Line 330, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 35574151550 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x61a7bac0
  UVM_INFO @ 35574151550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 14.rom_ctrl_stress_all_with_rand_reset.92262451684922497500173004421219064727052017783288230349301192992760251015301
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:39ef8310-3a4d-469d-9463-2b3f7b202a04
```
  - 36.rom_ctrl_stress_all_with_rand_reset.85563776865083653250286365997312829244387834632984072164470553531948796841257
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:20f4a703-7765-4ca7-b27c-304308e5ce7e
```
  - ... and 1 more failures.

ROM_CTRL/64KB Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: 6a84251492

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `6a84251492`