ROM_CTRL/64KB Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: `e439226b6c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.387m	16.483ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	37.180s	3.960ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	31.700s	17.806ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	30.600s	7.979ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	31.780s	18.577ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	32.040s	19.402ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	31.700s	17.806ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.780s	18.577ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	30.650s	4.339ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	27.770s	3.477ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	34.120s	18.202ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	4.047m	29.448ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.182m	35.417ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	32.530s	4.086ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	36.020s	64.031ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	36.020s	64.031ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	37.180s	3.960ms	5	5	100.00
		rom_ctrl_csr_rw	31.700s	17.806ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.780s	18.577ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	33.040s	34.921ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	37.180s	3.960ms	5	5	100.00
		rom_ctrl_csr_rw	31.700s	17.806ms	20	20	100.00
		rom_ctrl_csr_aliasing	31.780s	18.577ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	33.040s	34.921ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	15.107m	519.501ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.237m	98.718ms	19	20	95.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.151m	8.931ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.898m	4.092ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.151m	8.931ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.107m	519.501ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.107m	519.501ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	15.107m	519.501ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.107m	519.501ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.107m	519.501ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.151m	8.931ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.151m	8.931ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.387m	16.483ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.387m	16.483ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.387m	16.483ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.898m	4.092ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	15.107m	519.501ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.182m	35.417ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	15.107m	519.501ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	15.107m	519.501ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	15.107m	519.501ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.237m	98.718ms	19	20	95.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.151m	8.931ms	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.244h	81.539ms	5	50	10.00
V3		TOTAL			5	50	10.00
		TOTAL			453	500	90.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.26	96.89	91.99	97.68	100.00	98.62	97.30	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 33 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.25146559264942496384444818582099484393596235316119678593182990975895084370104
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 112338823 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 112338823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rom_ctrl_stress_all_with_rand_reset.18412016580774637835087677209914384116271022901231132300203525653179414029900
    Line 315, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 33490126764 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 33490126764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 31 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.12604772953709282552322170293846808780902920645359805337123626928561480835980
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:2f26df68-a237-48e5-ba6c-2f52d59c45f1
```
  - 12.rom_ctrl_stress_all_with_rand_reset.80517607071209011028161073253394873601469856836037425549731847259074519183480
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:5a085c7f-0afe-4485-95e8-09e4033111f0
```
  - ... and 6 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 26.rom_ctrl_stress_all_with_rand_reset.94570789813210640634111885353911285662269255239540595995641542654205705608481
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10003647396 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x9bf16114
  UVM_INFO @ 10003647396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.rom_ctrl_stress_all_with_rand_reset.17504493526669470409087632885482361760415592666166663099727744147979619834378
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10529682002 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x6cfa9ea0
  UVM_INFO @ 10529682002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 18.rom_ctrl_passthru_mem_tl_intg_err.28600336193984501278837530261474239306959994181979683596338656539470051681915
    Line 266, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 30.rom_ctrl_stress_all_with_rand_reset.77255301754068705796757427678540015806732906548687404384454200050869670759244
    Line 957, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 816858636333 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 816858636333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all has 1 failures.
  - 43.rom_ctrl_stress_all.12718070798443442583961866429477227426786877925789204279890220659892354031647
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40021528767 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x599ae6a
  UVM_INFO @ 40021528767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: e439226b6c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e439226b6c`