ROM_CTRL/64KB Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: `a47820eb4c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	37.430s	3.973ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	21.020s	3.947ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	10.080s	496.684us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	10.410s	253.245us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.040s	989.868us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.730s	14.306ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	10.080s	496.684us	20	20	100.00
		rom_ctrl_csr_aliasing	10.040s	989.868us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.580s	1.938ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	9.800s	253.893us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.130s	1.995ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.603m	9.330ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	32.600s	2.054ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	15.450s	1.020ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.450s	1.401ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.450s	1.401ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	21.020s	3.947ms	5	5	100.00
		rom_ctrl_csr_rw	10.080s	496.684us	20	20	100.00
		rom_ctrl_csr_aliasing	10.040s	989.868us	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.530s	3.950ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	21.020s	3.947ms	5	5	100.00
		rom_ctrl_csr_rw	10.080s	496.684us	20	20	100.00
		rom_ctrl_csr_aliasing	10.040s	989.868us	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.530s	3.950ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	11.515m	36.610ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.111m	3.048ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.791m	1.622ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.641m	431.286us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.791m	1.622ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	11.515m	36.610ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	11.515m	36.610ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	11.515m	36.610ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	11.515m	36.610ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	11.515m	36.610ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.791m	1.622ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.791m	1.622ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	37.430s	3.973ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	37.430s	3.973ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	37.430s	3.973ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.641m	431.286us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	11.515m	36.610ms	50	50	100.00
		rom_ctrl_kmac_err_chk	32.600s	2.054ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	11.515m	36.610ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	11.515m	36.610ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	11.515m	36.610ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.111m	3.048ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.791m	1.622ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.781h	168.828ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			469	500	93.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.31	96.89	92.13	97.68	100.00	98.62	97.45	98.37

Failure Buckets

Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 17 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 17 failures.
  - 5.rom_ctrl_stress_all_with_rand_reset.86435822076965730654624541682465020111819567141482680110563194144133411012557
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:34fbf12c-4e01-4d6e-9c00-f4cf388e6660
```
  - 7.rom_ctrl_stress_all_with_rand_reset.36259951103083343245979144777410575597820239560653000532880319878960558978175
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:3fd70d9a-57ba-46a3-8d53-9a0df5467446
```
  - ... and 15 more failures.
UVM_ERROR (cip_base_vseq.sv:839) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 13 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.60785513125338034882795249779143165029707060370599700646299265097718223482350
    Line 700, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 90447413299 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 90447413299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rom_ctrl_stress_all_with_rand_reset.34379289902494834961818672965551215680523016486608286478803260393665454368928
    Line 353, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 86716377341 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 86716377341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 39.rom_ctrl_stress_all_with_rand_reset.30062113844935057244971373947208661562588868491921963646129191845001028724951
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10017074920 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xb2ca961b
  UVM_INFO @ 10017074920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: a47820eb4c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `a47820eb4c`