ROM_CTRL/64KB Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: 4877b481e8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	38.120s	2.080ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.860s	516.434us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	10.010s	4.121ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	10.140s	4.957ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	9.850s	1.032ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.710s	4.166ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	10.010s	4.121ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.850s	1.032ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.660s	4.093ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	9.740s	507.000us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.250s	5.537ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.365m	19.712ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	32.790s	8.575ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	15.310s	2.047ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.830s	14.075ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.830s	14.075ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.860s	516.434us	5	5	100.00
		rom_ctrl_csr_rw	10.010s	4.121ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.850s	1.032ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.640s	4.114ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.860s	516.434us	5	5	100.00
		rom_ctrl_csr_rw	10.010s	4.121ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.850s	1.032ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.640s	4.114ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	10.475m	131.908ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.572m	31.288ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.786m	365.015us	5	5	100.00
		rom_ctrl_tl_intg_err	2.630m	2.243ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.786m	365.015us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.475m	131.908ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.475m	131.908ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	10.475m	131.908ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.475m	131.908ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.475m	131.908ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.786m	365.015us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.786m	365.015us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	38.120s	2.080ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	38.120s	2.080ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	38.120s	2.080ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.630m	2.243ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	10.475m	131.908ms	50	50	100.00
		rom_ctrl_kmac_err_chk	32.790s	8.575ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	10.475m	131.908ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.475m	131.908ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	10.475m	131.908ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.572m	31.288ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.786m	365.015us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.680h	32.460ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			467	500	93.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.28	96.89	92.13	97.68	100.00	98.62	97.30	98.37

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 20 failures.

    • 0.rom_ctrl_stress_all_with_rand_reset.82271183043526253606374832372824750259107643787522179711139722563017946328103
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 355067727 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 355067727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.rom_ctrl_stress_all_with_rand_reset.71809281077529880021624320122339424915047819982834830483478086598506202190544
      Line 438, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13790986048 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 13790986048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 13 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 13 failures.

    • 1.rom_ctrl_stress_all_with_rand_reset.35814242162444245739928310485626978740405552512736563601764940873544057276479
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:17531770-01bb-40be-9d20-ef894df5d763
      

    • 4.rom_ctrl_stress_all_with_rand_reset.21463546241045908924615447282663886875901953222566533997319349727934910942561
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:938dd6f8-8b96-49f2-b10e-724a720e9442
      

    • ... and 11 more failures.

Past Results

• Latest
• 2024.07.26_09.08.27
• 2024.07.25_08.39.50
• 2024.07.24_08.20.18
• 2024.07.23_08.52.50
• 2024.07.22_08.52.01
• 2024.07.21_08.32.36
• 2024.07.20_09.56.18