ROM_CTRL/64KB Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	36.830s	2.797ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.050s	253.193us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	10.000s	498.319us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	9.910s	506.163us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	9.910s	516.613us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	11.350s	528.371us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	10.000s	498.319us	20	20	100.00
		rom_ctrl_csr_aliasing	9.910s	516.613us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	8.250s	873.164us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	9.790s	361.812us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.280s	4.143ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.177m	6.943ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	32.550s	10.939ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	15.330s	3.935ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.160s	984.300us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.160s	984.300us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.050s	253.193us	5	5	100.00
		rom_ctrl_csr_rw	10.000s	498.319us	20	20	100.00
		rom_ctrl_csr_aliasing	9.910s	516.613us	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.930s	2.054ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.050s	253.193us	5	5	100.00
		rom_ctrl_csr_rw	10.000s	498.319us	20	20	100.00
		rom_ctrl_csr_aliasing	9.910s	516.613us	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.930s	2.054ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	6.750m	398.006ms	49	50	98.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.108m	1.621ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.052m	2.384ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.654m	1.501ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.052m	2.384ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.750m	398.006ms	49	50	98.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.750m	398.006ms	49	50	98.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	6.750m	398.006ms	49	50	98.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.750m	398.006ms	49	50	98.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.750m	398.006ms	49	50	98.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.052m	2.384ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.052m	2.384ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	36.830s	2.797ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	36.830s	2.797ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	36.830s	2.797ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.654m	1.501ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	6.750m	398.006ms	49	50	98.00
		rom_ctrl_kmac_err_chk	32.550s	10.939ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	6.750m	398.006ms	49	50	98.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.750m	398.006ms	49	50	98.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	6.750m	398.006ms	49	50	98.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.108m	1.621ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.052m	2.384ms	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.261h	89.197ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			466	500	93.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.21	96.89	91.99	97.68	100.00	98.28	97.30	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 17 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.95233712327359404791199185576513200411434620576804494800724922056552529454633
    Line 321, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13580389583 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 13580389583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.114156955843589101292462511504098985479708033299843103185634342807830668689174
    Line 688, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 48587949272 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 48587949272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 16 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 16 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.49913514248289719688312518628699129736818634051027977057905155347236172927074
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:d2e6d626-8dd9-41c7-a04f-9e5d0e62ec2f
```
  - 9.rom_ctrl_stress_all_with_rand_reset.26621092998559680992316632165940204222162543918243479923669792540646341173166
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c1b1cdfa-86d0-4d7e-ac16-3c2937f6c2cc
```
  - ... and 14 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 40.rom_ctrl_corrupt_sig_fatal_chk.54761204813489543367989158688737181148103636825896680891897956039785562718823
    Line 293, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 398005682974 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 398005682974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `eca25c0ff8`