ROM_CTRL/64KB Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	36.470s	2.047ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.720s	3.148ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.130s	1.021ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	10.350s	1.124ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.100s	2.755ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.020s	1.989ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.130s	1.021ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.100s	2.755ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	9.950s	1.033ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	10.020s	249.710us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.180s	1.013ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.272m	1.620ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	32.960s	6.597ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	15.200s	2.110ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.380s	1.227ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.380s	1.227ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.720s	3.148ms	5	5	100.00
		rom_ctrl_csr_rw	15.130s	1.021ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.100s	2.755ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	13.900s	2.091ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.720s	3.148ms	5	5	100.00
		rom_ctrl_csr_rw	15.130s	1.021ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.100s	2.755ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	13.900s	2.091ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.470m	8.630ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.633m	66.039ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.396m	620.917us	5	5	100.00
		rom_ctrl_tl_intg_err	2.692m	629.237us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.396m	620.917us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.470m	8.630ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.470m	8.630ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.470m	8.630ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.470m	8.630ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.470m	8.630ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.396m	620.917us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.396m	620.917us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	36.470s	2.047ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	36.470s	2.047ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	36.470s	2.047ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.692m	629.237us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.470m	8.630ms	50	50	100.00
		rom_ctrl_kmac_err_chk	32.960s	6.597ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.470m	8.630ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.470m	8.630ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.470m	8.630ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.633m	66.039ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.396m	620.917us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.636h	33.377ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			470	500	94.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.34	96.89	91.99	97.68	100.00	98.28	97.45	99.07

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 19 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.88744946814076038898063227551432782905027377657402312154455347048732890411207
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 115817485 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 115817485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rom_ctrl_stress_all_with_rand_reset.42555382592107575597117258652329916337908680302703079304706322133347542051073
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 112138594 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 112138594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 10 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 10 failures.
  - 7.rom_ctrl_stress_all_with_rand_reset.94578082019783366503449087944053439272674055764070722947591652023565708404840
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:85a8fdc0-aaa4-4941-96c9-8df8a7a41a6f
```
  - 11.rom_ctrl_stress_all_with_rand_reset.35300267824320258172428243200457345000564373174779404727564764287765139644020
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:7378016d-05b7-442e-babd-9ad90909e297
```
  - ... and 8 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_stress_all has 1 failures.
  - 30.rom_ctrl_stress_all.70073364658262004053253917896882084421597078872095200192935632484937530007647
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 3423416096 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 3423416096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `eca25c0ff8`