ROM_CTRL/64KB Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: `39f3866b56`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	16.790s	1.028ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.130s	2.769ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	10.050s	257.151us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	10.660s	260.771us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	9.670s	3.536ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	11.940s	274.312us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	10.050s	257.151us	20	20	100.00
		rom_ctrl_csr_aliasing	9.670s	3.536ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	15.140s	2.051ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	9.510s	1.035ms	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	16.870s	997.065us	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	52.730s	2.228ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	32.950s	1.970ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	14.970s	1.027ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	17.980s	6.990ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	17.980s	6.990ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.130s	2.769ms	5	5	100.00
		rom_ctrl_csr_rw	10.050s	257.151us	20	20	100.00
		rom_ctrl_csr_aliasing	9.670s	3.536ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.370s	997.434us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.130s	2.769ms	5	5	100.00
		rom_ctrl_csr_rw	10.050s	257.151us	20	20	100.00
		rom_ctrl_csr_aliasing	9.670s	3.536ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.370s	997.434us	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.249m	24.808ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	57.370s	1.821ms	7	20	35.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.795m	1.480ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.660m	847.899us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.795m	1.480ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.249m	24.808ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.249m	24.808ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.249m	24.808ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.249m	24.808ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.249m	24.808ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.795m	1.480ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.795m	1.480ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	16.790s	1.028ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	16.790s	1.028ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	16.790s	1.028ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.660m	847.899us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.249m	24.808ms	50	50	100.00
		rom_ctrl_kmac_err_chk	32.950s	1.970ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.249m	24.808ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.249m	24.808ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.249m	24.808ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	57.370s	1.821ms	7	20	35.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.795m	1.480ms	5	5	100.00
V2S		TOTAL			82	95	86.32
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.756h	465.761ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			410	460	89.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.41	96.89	92.56	97.68	100.00	98.97	97.45	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 15 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.92060156238269321363566715186430089589953642239251426041852346040395769765820
    Line 837, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 909234639809 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 909234639809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.rom_ctrl_stress_all_with_rand_reset.57137062989029874603903692888543746394782610326448584361600986613320206590702
    Line 390, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 81258520545 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 81258520545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_*' while it is being accessed has 11 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 11 failures.

0.rom_ctrl_passthru_mem_tl_intg_err.54175725941404345217170118211876209889749946856955760218844370409227312605875
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 1032112072 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 1032112072 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 1032112072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.rom_ctrl_passthru_mem_tl_intg_err.29681558046516139803807732149518278238122960579648022350111023763331147874313
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 688237755 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 688237755 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 688237755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.95409285092000529402046731088915465916374228774753863118262806353893234303927
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c6230762-6d5f-4229-ae64-e9a1a29302d1
```
  - 6.rom_ctrl_stress_all_with_rand_reset.36721326019427896657701948837855225235485397171584042984421816187274603314959
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:b174a1ac-ab0d-453b-bbe9-791ace321707
```
  - ... and 5 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.98312576668079926612647418109246057033837212231744083853046941787923024429459
    Line 393, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11830120651 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 11830120651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.rom_ctrl_stress_all_with_rand_reset.99749910297307113165506552404394753727591454216479926256293813261806416777599
    Line 341, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 45218641798 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 45218641798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 3.rom_ctrl_stress_all_with_rand_reset.50605217683981724777976524179653315013109829149524839709709281974963341059013
    Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 698315600 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 698315600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.rom_ctrl_stress_all_with_rand_reset.17146982358918710675772596114203300955081382720687981109120933188857774426145
    Line 344, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 13623772023 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 13623772023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_*' while it is being accessed has 2 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 2 failures.

11.rom_ctrl_passthru_mem_tl_intg_err.64477974541589104369447084499093514485059947783112355735505538276471505700473
Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 1507121884 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_0' while it is being accessed
  UVM_ERROR @ 1507121884 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 1507121884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.rom_ctrl_passthru_mem_tl_intg_err.53592861435701315541593288295430559741338682216572441260881519668567361898164
Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 650909508 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_1' while it is being accessed
  UVM_ERROR @ 650909508 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 650909508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rom_ctrl_base_vseq.sv:91) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 47.rom_ctrl_stress_all_with_rand_reset.19382237090303895888428713944319316331370125333231984335563656756442897746865
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 273860681 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 273860681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```