ROM_CTRL/64KB Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: `fdfa12db04`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	17.920s	1.008ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.690s	527.666us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	10.170s	1.460ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	10.420s	992.663us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.190s	514.812us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.120s	1.986ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	10.170s	1.460ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.190s	514.812us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	10.080s	259.949us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	10.020s	259.375us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.030s	1.084ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	48.160s	1.039ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	33.170s	3.954ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	10.580s	1.031ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	15.490s	259.851us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	15.490s	259.851us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.690s	527.666us	5	5	100.00
		rom_ctrl_csr_rw	10.170s	1.460ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.190s	514.812us	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.080s	2.053ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.690s	527.666us	5	5	100.00
		rom_ctrl_csr_rw	10.170s	1.460ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.190s	514.812us	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.080s	2.053ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	9.780m	110.060ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	45.120s	1.041ms	4	20	20.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.823m	492.584us	5	5	100.00
		rom_ctrl_tl_intg_err	2.844m	4.414ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.823m	492.584us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.780m	110.060ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.780m	110.060ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.780m	110.060ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.780m	110.060ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.780m	110.060ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.823m	492.584us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.823m	492.584us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	17.920s	1.008ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	17.920s	1.008ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	17.920s	1.008ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.844m	4.414ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.780m	110.060ms	50	50	100.00
		rom_ctrl_kmac_err_chk	33.170s	3.954ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	9.780m	110.060ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.780m	110.060ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	9.780m	110.060ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	45.120s	1.041ms	4	20	20.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.823m	492.584us	5	5	100.00
V2S		TOTAL			79	95	83.16
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.696h	26.897ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			410	460	89.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.30	96.89	92.28	97.68	100.00	98.62	97.30	98.37

Failure Buckets

Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 18 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 18 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.72302841598666671906145856241150014640490990761304236250043311590228177176636
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:13c232ff-b4f6-47bb-a921-87c8408fb9c4
```
  - 5.rom_ctrl_stress_all_with_rand_reset.104123875275812953238043399382741845556826950121588003075145921612954040096675
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:1933cf08-5933-443b-bac4-95e652cc1923
```
  - ... and 16 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_*' while it is being accessed

has 10 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 10 failures.

1.rom_ctrl_passthru_mem_tl_intg_err.82527261904780477800880922356377880147046856268898494040821062079319208575422
Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 341500177 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 341500177 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 341500177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.rom_ctrl_passthru_mem_tl_intg_err.19329553184942924144867980344597269672563794781151744164400787946917607438161
Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 860880633 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 860880633 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 860880633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 10 failures.
  - 3.rom_ctrl_stress_all_with_rand_reset.66972924029246269641612242989058071614333771108390792935609566254702650597727
    Line 340, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7028566438 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7028566438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.rom_ctrl_stress_all_with_rand_reset.113159260876815565764511686410612005645701482221481856099523898947249008901745
    Line 581, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21915201330 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 21915201330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_*' while it is being accessed

has 6 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 6 failures.

4.rom_ctrl_passthru_mem_tl_intg_err.112665521196089943801013880254143694973972877189743670058350335834138369699075
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 989345168 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_0' while it is being accessed
  UVM_ERROR @ 989345168 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 989345168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.rom_ctrl_passthru_mem_tl_intg_err.10939974498769497438889292126724410409407126755907465553046177420636326275080
Line 261, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 680441982 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_0' while it is being accessed
  UVM_ERROR @ 680441982 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 680441982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 7.rom_ctrl_stress_all_with_rand_reset.44397196443867597441497822502315978661420233288820368510457023477135337260041
    Line 363, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 26587351766 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 26587351766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.rom_ctrl_stress_all_with_rand_reset.10794611874053634824916496918650273912553629607753505708273593772117547723092
    Line 668, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 164597096470 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 164597096470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 31.rom_ctrl_stress_all_with_rand_reset.58641724061771296091485374730950037797146427530630962295392286699467897095139
    Line 710, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 96397755351 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 96397755351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.rom_ctrl_stress_all_with_rand_reset.12362666777098071293237193633912708136608911172661647332155839326046801995800
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5009998233 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 5009998233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.