ROM_CTRL/64KB Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: `e9b7e615a7`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	12.550s	1.068ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.490s	278.346us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	10.240s	1.029ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.550s	989.733us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	14.920s	4.113ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.460s	1.013ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	10.240s	1.029ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.920s	4.113ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	9.840s	508.253us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	9.860s	507.158us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	16.550s	989.552us	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.144m	19.792ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	33.530s	2.027ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	10.870s	507.358us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.520s	1.028ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.520s	1.028ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.490s	278.346us	5	5	100.00
		rom_ctrl_csr_rw	10.240s	1.029ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.920s	4.113ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.690s	2.015ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.490s	278.346us	5	5	100.00
		rom_ctrl_csr_rw	10.240s	1.029ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.920s	4.113ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.690s	2.015ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.155m	42.420ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	57.730s	1.069ms	3	20	15.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.817m	449.274us	5	5	100.00
		rom_ctrl_tl_intg_err	2.648m	787.219us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.817m	449.274us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.155m	42.420ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.155m	42.420ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.155m	42.420ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.155m	42.420ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.155m	42.420ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.817m	449.274us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.817m	449.274us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	12.550s	1.068ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	12.550s	1.068ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	12.550s	1.068ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.648m	787.219us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.155m	42.420ms	50	50	100.00
		rom_ctrl_kmac_err_chk	33.530s	2.027ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.155m	42.420ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.155m	42.420ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.155m	42.420ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	57.730s	1.069ms	3	20	15.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.817m	449.274us	5	5	100.00
V2S		TOTAL			78	95	82.11
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.781h	138.320ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			408	460	88.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.26	96.89	91.99	97.68	100.00	98.62	97.30	98.37

Failure Buckets

Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 18 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 18 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.6997362377990681376247939839775499388897241106180774100391061882230085433378
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:d27a1f73-7863-44d0-899d-63083d4a2c5b
```
  - 5.rom_ctrl_stress_all_with_rand_reset.109876981647358391173215617338958013092038298914120974423419432145396815050121
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:bbc5e627-5648-4798-ae5e-c60cd93fad1e
```
  - ... and 16 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_*' while it is being accessed

has 13 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 13 failures.

0.rom_ctrl_passthru_mem_tl_intg_err.16835166557042343477047695096370144802609101149326259650167712084275074830421
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 250867701 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 250867701 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 250867701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_ctrl_passthru_mem_tl_intg_err.44076004595093487076332645804405104940258521879054238111535388125742207746879
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 659446978 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 659446978 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 659446978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.111999765641438788477805451586028497759060971836877295521155781952807625885333
    Line 338, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9430832629 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9430832629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.rom_ctrl_stress_all_with_rand_reset.81392658474641663260138763456156234574608260154774855433490242833401392293062
    Line 465, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 138319588187 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 138319588187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.65394478375213529923215538560490932555418946813129658138644214338669012877436
    Line 333, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6903715528 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 6903715528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.rom_ctrl_stress_all_with_rand_reset.66236634718775000002344863467977132241329939810979110306251683017059731266932
    Line 334, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9546592943 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 9546592943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_*' while it is being accessed

has 4 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 4 failures.

3.rom_ctrl_passthru_mem_tl_intg_err.72316339746104397309677548434021746921311720014898777414173098728217701343931
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 514399733 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_1' while it is being accessed
  UVM_ERROR @ 514399733 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 514399733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.rom_ctrl_passthru_mem_tl_intg_err.40075341321484272406737599562633605585902629741232121390914416262598264398556
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 247242480 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_0' while it is being accessed
  UVM_ERROR @ 247242480 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 247242480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.44303571979777047774717975965966245053674977847342287465429612907074030248393
    Line 437, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 20300448992 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 20300448992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.rom_ctrl_stress_all_with_rand_reset.10945575880826599571216471802627137976785002695652890305827657229362962232905
    Line 358, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11938334534 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 11938334534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```