ROM_CTRL/64KB Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: `625f353e9c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	12.860s	525.392us	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.220s	1.049ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	10.110s	1.648ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	10.200s	1.031ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	9.860s	638.345us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	11.240s	520.585us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	10.110s	1.648ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.860s	638.345us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	9.860s	260.656us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	9.570s	988.235us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	16.780s	2.076ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.348m	12.114ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	33.080s	9.798ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	15.110s	981.739us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.040s	1.078ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.040s	1.078ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.220s	1.049ms	5	5	100.00
		rom_ctrl_csr_rw	10.110s	1.648ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.860s	638.345us	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.150s	994.461us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.220s	1.049ms	5	5	100.00
		rom_ctrl_csr_rw	10.110s	1.648ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.860s	638.345us	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.150s	994.461us	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	6.192m	12.936ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	57.590s	2.155ms	3	20	15.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.775m	419.812us	5	5	100.00
		rom_ctrl_tl_intg_err	2.674m	1.265ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.775m	419.812us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.192m	12.936ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.192m	12.936ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	6.192m	12.936ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.192m	12.936ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.192m	12.936ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.775m	419.812us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.775m	419.812us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	12.860s	525.392us	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	12.860s	525.392us	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	12.860s	525.392us	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.674m	1.265ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	6.192m	12.936ms	50	50	100.00
		rom_ctrl_kmac_err_chk	33.080s	9.798ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	6.192m	12.936ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.192m	12.936ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	6.192m	12.936ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	57.590s	2.155ms	3	20	15.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.775m	419.812us	5	5	100.00
V2S		TOTAL			78	95	82.11
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.890h	24.462ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			407	460	88.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.21	96.89	91.99	97.68	100.00	98.28	97.30	98.37

Failure Buckets

Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 15 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 15 failures.
  - 3.rom_ctrl_stress_all_with_rand_reset.63106423986498612081229636590295027589119098319220433249399630240434474567270
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:94cf1c93-6669-444d-bce6-0a4f9e07762e
```
  - 4.rom_ctrl_stress_all_with_rand_reset.4997205945611479892681087385896130756658317825127612601405242075365084705576
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:93f21619-459b-42c3-9ff1-1dd691946ebd
```
  - ... and 13 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 13 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.48119342052825330467503090922116509249817111665034863130252265715442964850226
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 228334960 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 228334960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.rom_ctrl_stress_all_with_rand_reset.5762087649957150127386987088855002551393099990847529391836103942434154117182
    Line 363, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25149562742 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 25149562742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_*' while it is being accessed has 12 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 12 failures.

1.rom_ctrl_passthru_mem_tl_intg_err.337532687922602000252266345084908016440841880810860887416227536927948947596
Line 264, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 3419677695 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 3419677695 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 3419677695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.rom_ctrl_passthru_mem_tl_intg_err.67988183789809667384721753229219393236601694170972216695230231183299682209636
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 982905957 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 982905957 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 982905957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_*' while it is being accessed has 5 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 5 failures.

0.rom_ctrl_passthru_mem_tl_intg_err.1136581840268956731098839375088989748780833575844619320700678764930165380743
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 989734479 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_0' while it is being accessed
  UVM_ERROR @ 989734479 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 989734479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.rom_ctrl_passthru_mem_tl_intg_err.47017884482201511562511985015097329018148850308773695277666124151725017194906
Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 1041048964 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_0' while it is being accessed
  UVM_ERROR @ 1041048964 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 1041048964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.63347750227366467481665767458338211821517452831737180708201189871539511827607
    Line 273, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1025027472 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1025027472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.rom_ctrl_stress_all_with_rand_reset.93489812891636402647353690468526744084166850722916076808249037183482199246696
    Line 346, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7880053917 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 7880053917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 17.rom_ctrl_stress_all_with_rand_reset.4435702615652086691791393630549771717168711647825692014662401603751901609893
    Line 382, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 48451236962 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 48451236962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:247) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_kmac_err_chk has 1 failures.
  - 22.rom_ctrl_kmac_err_chk.33471853574874781748558958033564840609995911095832799754298045295750573393944
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 5493577518 ps: (rom_ctrl_scoreboard.sv:247) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 5493577518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_base_vseq.sv:91) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 25.rom_ctrl_stress_all_with_rand_reset.31504578731426490823150185957802955114513035425750762179829478688343114970513
    Line 290, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5510892685 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 5510892685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```