ROM_CTRL/64KB Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	17.790s	1.057ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.260s	259.573us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.400s	2.408ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.490s	4.124ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	9.940s	988.268us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.080s	2.029ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.400s	2.408ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.940s	988.268us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	9.960s	256.948us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	9.950s	587.791us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.010s	4.750ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	59.000s	16.680ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	33.660s	2.119ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	15.250s	1.045ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	17.980s	1.020ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	17.980s	1.020ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.260s	259.573us	5	5	100.00
		rom_ctrl_csr_rw	14.400s	2.408ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.940s	988.268us	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.800s	2.810ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.260s	259.573us	5	5	100.00
		rom_ctrl_csr_rw	14.400s	2.408ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.940s	988.268us	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.800s	2.810ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	6.822m	8.011ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	56.270s	4.923ms	5	20	25.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.815m	1.911ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.608m	510.613us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.815m	1.911ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.822m	8.011ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.822m	8.011ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	6.822m	8.011ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.822m	8.011ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.822m	8.011ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.815m	1.911ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.815m	1.911ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	17.790s	1.057ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	17.790s	1.057ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	17.790s	1.057ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.608m	510.613us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	6.822m	8.011ms	50	50	100.00
		rom_ctrl_kmac_err_chk	33.660s	2.119ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	6.822m	8.011ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.822m	8.011ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	6.822m	8.011ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	56.270s	4.923ms	5	20	25.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.815m	1.911ms	5	5	100.00
V2S		TOTAL			80	95	84.21
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.916h	49.462ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			410	460	89.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.16	96.89	91.85	97.68	100.00	98.28	97.30	98.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 16 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.99629567382811064556644999246253880814576841559873926306900185601627250379080
    Line 336, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5926069378 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5926069378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.21303918487245300150426470132670113044187984657195082704945820387614435343458
    Line 261, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 120481882 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 120481882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_*' while it is being accessed has 13 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 13 failures.

3.rom_ctrl_passthru_mem_tl_intg_err.16515828534574013803148051244881656276736774035155682810582033303950167960796
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 2066055187 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 2066055187 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 2066055187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.rom_ctrl_passthru_mem_tl_intg_err.54338476490626467833307567889662433629942450818215957604656006083720529787068
Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 650066622 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 650066622 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 650066622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.110416130776755692778825619132511561203939482762740442863022623004197694162140
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:add8e37b-ac4b-44d2-a161-f67e941e7fcc
```
  - 10.rom_ctrl_stress_all_with_rand_reset.53644230908195478877922630018099927656864605879264201653509089688766899410682
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:17c029cb-b2dd-415d-a619-8000ac5399e6
```
  - ... and 6 more failures.
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 4 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 4 failures.
  - 7.rom_ctrl_stress_all_with_rand_reset.6638694224666315810079001143007639833943898686556236412403284878022693182395
    Line 481, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 92279840259 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 92279840259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.rom_ctrl_stress_all_with_rand_reset.102208918492549561980080721727305320127064846701553893011189493373532206151652
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 242737683 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 242737683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 4 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 4 failures.
  - 18.rom_ctrl_stress_all_with_rand_reset.53871419877228278505385592582138174737726141937206626356478211666966887422977
    Line 1068, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 357825173496 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 357825173496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.rom_ctrl_stress_all_with_rand_reset.77271512192006826896196627656518836024575986157921637278684142395038358215922
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1006349464 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1006349464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_*' while it is being accessed has 2 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 2 failures.

1.rom_ctrl_passthru_mem_tl_intg_err.109797126162667407540194229345514261278427486609666271120617354825152135930978
Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 2579692709 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_0' while it is being accessed
  UVM_ERROR @ 2579692709 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 2579692709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.rom_ctrl_passthru_mem_tl_intg_err.77841900673518766391351887697284130557942788084603198852622926740378192393466
Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 2083430327 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_1' while it is being accessed
  UVM_ERROR @ 2083430327 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 2083430327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rom_ctrl_base_vseq.sv:91) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 27.rom_ctrl_stress_all_with_rand_reset.74393882646797160165865189057677368583247531621119374469860817688047897407563
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1217804958 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1217804958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.rom_ctrl_stress_all_with_rand_reset.12619136687916169357403934296486952344492421717425760016100575522222903753110
    Line 316, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26414588439 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 26414588439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:247) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_kmac_err_chk has 1 failures.
  - 45.rom_ctrl_kmac_err_chk.101305475533230565273674335380960549822014327186613292265591516908180778214671
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 6591110256 ps: (rom_ctrl_scoreboard.sv:247) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 6591110256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```