ROM_CTRL/64KB Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	19.360s	4.172ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	18.460s	19.911ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	10.180s	4.960ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	9.950s	988.930us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.230s	336.738us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	11.320s	917.302us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	10.180s	4.960ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.230s	336.738us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	15.040s	7.068ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	9.990s	1.032ms	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.200s	3.969ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	58.130s	1.329ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	33.400s	8.234ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	15.060s	1.889ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	15.160s	527.195us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	15.160s	527.195us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	18.460s	19.911ms	5	5	100.00
		rom_ctrl_csr_rw	10.180s	4.960ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.230s	336.738us	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.350s	2.074ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	18.460s	19.911ms	5	5	100.00
		rom_ctrl_csr_rw	10.180s	4.960ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.230s	336.738us	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.350s	2.074ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.393m	87.017ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	56.240s	4.305ms	5	20	25.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.853m	2.246ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.612m	1.236ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.853m	2.246ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.393m	87.017ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.393m	87.017ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.393m	87.017ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.393m	87.017ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.393m	87.017ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.853m	2.246ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.853m	2.246ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	19.360s	4.172ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	19.360s	4.172ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	19.360s	4.172ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.612m	1.236ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.393m	87.017ms	50	50	100.00
		rom_ctrl_kmac_err_chk	33.400s	8.234ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.393m	87.017ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.393m	87.017ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.393m	87.017ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	56.240s	4.305ms	5	20	25.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.853m	2.246ms	5	5	100.00
V2S		TOTAL			80	95	84.21
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.687h	104.493ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			415	460	90.22

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.26	96.89	92.42	97.68	100.00	98.62	97.30	97.90

Failure Buckets

Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 18 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 18 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.34008117975700222471897395940428687866444732903310719536300387812966445078302
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:1142c64c-2b4a-4034-9c45-e3090c0d9b75
```
  - 5.rom_ctrl_stress_all_with_rand_reset.61777721937381572452365497662581613627197358436154423474788116161846472097440
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:63bddf05-ca7f-4f50-9638-ee870fea1902
```
  - ... and 16 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_*' while it is being accessed

has 12 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 12 failures.

2.rom_ctrl_passthru_mem_tl_intg_err.45706656922127565312766711614909226428594498428216897347403034604329236315641
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 252438737 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 252438737 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 252438737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.rom_ctrl_passthru_mem_tl_intg_err.73763706068442572305821415234562718443709661951109164350429487646693599384640
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 589627932 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 589627932 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 589627932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 11 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 11 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.103482840842654356643456097100937876447590763697271532021892262619758828353905
    Line 424, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 143677833233 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 143677833233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.rom_ctrl_stress_all_with_rand_reset.95658798268351184491418039416534749712887752589151461804100512756122193724951
    Line 347, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36353054830 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 36353054830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_*' while it is being accessed

has 3 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 3 failures.

1.rom_ctrl_passthru_mem_tl_intg_err.45273066796650860692836635625247701731467744759679214555083653296807540990508
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 3093466106 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_1' while it is being accessed
  UVM_ERROR @ 3093466106 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 3093466106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.rom_ctrl_passthru_mem_tl_intg_err.102777046686127685752648022554479939884445318023157836348871759983915684719838
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 1549288867 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_0' while it is being accessed
  UVM_ERROR @ 1549288867 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 1549288867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 39.rom_ctrl_stress_all_with_rand_reset.53778393978922497148556016898521247169650593178102464328192336844950806376116
    Line 317, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 13368742929 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 13368742929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```