ROM_CTRL/64KB Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	12.760s	1.069ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.420s	902.841us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.330s	2.021ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	8.850s	691.214us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.370s	251.760us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.980s	19.811ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.330s	2.021ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.370s	251.760us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	10.270s	257.444us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	14.100s	4.096ms	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.210s	14.220ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	49.060s	11.885ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	32.510s	3.938ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	15.380s	1.046ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	17.650s	1.019ms	19	20	95.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	17.650s	1.019ms	19	20	95.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.420s	902.841us	5	5	100.00
		rom_ctrl_csr_rw	14.330s	2.021ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.370s	251.760us	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.310s	3.407ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.420s	902.841us	5	5	100.00
		rom_ctrl_csr_rw	14.330s	2.021ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.370s	251.760us	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.310s	3.407ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.046m	82.767ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	43.830s	4.194ms	2	20	10.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.805m	1.323ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.632m	1.901ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.805m	1.323ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.046m	82.767ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.046m	82.767ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.046m	82.767ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.046m	82.767ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.046m	82.767ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.805m	1.323ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.805m	1.323ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	12.760s	1.069ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	12.760s	1.069ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	12.760s	1.069ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.632m	1.901ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.046m	82.767ms	50	50	100.00
		rom_ctrl_kmac_err_chk	32.510s	3.938ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.046m	82.767ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.046m	82.767ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.046m	82.767ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	43.830s	4.194ms	2	20	10.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.805m	1.323ms	5	5	100.00
V2S		TOTAL			77	95	81.05
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.980h	102.764ms	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			402	460	87.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.13	96.89	91.85	97.68	100.00	98.28	97.30	97.90

Failure Buckets

Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 19 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 19 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.72590650222838998913063419869727595882094504873107396402507830717189562201708
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:ff42caf0-4def-4ce0-8b7b-d17b7d53aee5
```
  - 1.rom_ctrl_stress_all_with_rand_reset.94987177466317065860409367161567312853288836381872619486471937710839043890003
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:12f30a9a-a0be-415d-ac0e-3e7ee843722d
```
  - ... and 17 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_*' while it is being accessed has 17 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 17 failures.

0.rom_ctrl_passthru_mem_tl_intg_err.44213224965672564648687902628091245985009991196669851559670439110576263304156
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 2736226793 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 2736226793 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 2736226793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_ctrl_passthru_mem_tl_intg_err.85748024869352329384694905060427349256809821154324769855565024281212659598982
Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 812217622 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 812217622 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 812217622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 15 more failures.

UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 13 failures.
  - 10.rom_ctrl_stress_all_with_rand_reset.63925892803023155242027378631289701197521857036939338297399234057946715527773
    Line 477, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26338027586 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 26338027586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.rom_ctrl_stress_all_with_rand_reset.62764599950497044273139114252761045185584940941199656427497249328969737249540
    Line 357, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12142173500 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 12142173500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 5.rom_ctrl_stress_all_with_rand_reset.81330923823353783789556546267031136312857913803029413965754760599945026620980
    Line 341, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9104996430 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 9104996430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.rom_ctrl_stress_all_with_rand_reset.65818979965691862272189608446424848902687640888537001345892175850152862036479
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 169125371 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 169125371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:91) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 11.rom_ctrl_stress_all_with_rand_reset.110220254556042316678454426953054346846849420467680454359667150772392302246597
    Line 977, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 158192802249 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 158192802249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.rom_ctrl_stress_all_with_rand_reset.67963573601570735464667860500648968159072553448916723871920268546638538027426
    Line 389, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 52515482729 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 52515482729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 44.rom_ctrl_stress_all_with_rand_reset.37324562081185544592366360832364481072493611803972612298671709245257611005148
    Line 271, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3419032698 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 3419032698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.rom_ctrl_stress_all_with_rand_reset.15668066909859111123552309707481988248014660676266713844133152570472649282021
    Line 384, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 54902498150 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 54902498150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_*' while it is being accessed has 1 failures:
- Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 7.rom_ctrl_passthru_mem_tl_intg_err.22217643058095584508016107706200302534646790175304055410909103351165437866871
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_WARNING @ 688111696 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_0' while it is being accessed
  UVM_ERROR @ 688111696 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 688111696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:247) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_tl_errors has 1 failures.
  - 13.rom_ctrl_tl_errors.104658700436343410442060310486481756104865545817175158522780253848872609163452
    Line 253, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_tl_errors/latest/run.log
```
  UVM_ERROR @ 3298248645 ps: (rom_ctrl_scoreboard.sv:247) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 3298248645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```