ROM_CTRL/64KB Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: `e4c5daa580`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	16.790s	2.009ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.180s	511.204us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.070s	995.554us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	10.110s	498.486us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	8.630s	183.847us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	11.440s	262.065us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.070s	995.554us	20	20	100.00
		rom_ctrl_csr_aliasing	8.630s	183.847us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	10.060s	519.737us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	9.950s	506.078us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.120s	1.177ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	54.800s	1.822ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	30.970s	2.434ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	15.520s	3.814ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.060s	6.124ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.060s	6.124ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.180s	511.204us	5	5	100.00
		rom_ctrl_csr_rw	15.070s	995.554us	20	20	100.00
		rom_ctrl_csr_aliasing	8.630s	183.847us	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.090s	259.888us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.180s	511.204us	5	5	100.00
		rom_ctrl_csr_rw	15.070s	995.554us	20	20	100.00
		rom_ctrl_csr_aliasing	8.630s	183.847us	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.090s	259.888us	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.814m	49.677ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	45.080s	1.030ms	4	20	20.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.817m	604.087us	5	5	100.00
		rom_ctrl_tl_intg_err	2.629m	419.401us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.817m	604.087us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.814m	49.677ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.814m	49.677ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.814m	49.677ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.814m	49.677ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.814m	49.677ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.817m	604.087us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.817m	604.087us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	16.790s	2.009ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	16.790s	2.009ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	16.790s	2.009ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.629m	419.401us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.814m	49.677ms	50	50	100.00
		rom_ctrl_kmac_err_chk	30.970s	2.434ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.814m	49.677ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.814m	49.677ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.814m	49.677ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	45.080s	1.030ms	4	20	20.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.817m	604.087us	5	5	100.00
V2S		TOTAL			79	95	83.16
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.537h	97.953ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			409	460	88.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.21	96.89	91.99	97.68	100.00	98.28	97.30	98.37

Failure Buckets

Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 15 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 15 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.17190309822007253521526060917345855170836080361294701875751820027508718841873
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:39f038e2-a50d-40ff-af2f-fecf89ec4ab0
```
  - 7.rom_ctrl_stress_all_with_rand_reset.91649558002369550185956806380942777807208406646360760760494606440592123733793
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:8de502bb-d80b-40b2-bde0-b491ea540334
```
  - ... and 13 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 14 failures.
  - 5.rom_ctrl_stress_all_with_rand_reset.91979769972790194487525265624111527091383475274663912976392335526980508629549
    Line 305, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4944456181 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4944456181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.rom_ctrl_stress_all_with_rand_reset.11874850780487119446489763607758515455028980372261194885800582630732843119824
    Line 300, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1979905882 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1979905882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_*' while it is being accessed has 10 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 10 failures.

2.rom_ctrl_passthru_mem_tl_intg_err.16706934324150934231280653701920804005534738915513198653132179888445259503921
Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 10030670184 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 10030670184 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 10030670184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.rom_ctrl_passthru_mem_tl_intg_err.78561293311377912978880039237340722518885529422975671525167853464845046726212
Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 3010087428 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_1' while it is being accessed
  UVM_ERROR @ 3010087428 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 3010087428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_*' while it is being accessed has 6 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 6 failures.

0.rom_ctrl_passthru_mem_tl_intg_err.35829771605096670618842762210132240950538296615053212188194101777607875696401
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 4122474187 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_3' while it is being accessed
  UVM_ERROR @ 4122474187 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 4122474187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.rom_ctrl_passthru_mem_tl_intg_err.64596294755796265466609027856430662751614161515106832101518117229140976284994
Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 518689376 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_0' while it is being accessed
  UVM_ERROR @ 518689376 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 518689376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.8140767490707270914195420044214287108352770972218798928894582194435455016827
    Line 334, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19753212552 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 19753212552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.rom_ctrl_stress_all_with_rand_reset.95997258759738951397305540163463975698442933378171746408692977842403076542595
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1006024434 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1006024434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.34773427967880775706584049365867324569583301099466902447036748238355321694977
    Line 332, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 38312821021 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 38312821021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.rom_ctrl_stress_all_with_rand_reset.76383197253041470587162987999219194547502957730645579681113740900963269000722
    Line 357, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 49841268886 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 49841268886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:247) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_kmac_err_chk has 1 failures.
  - 46.rom_ctrl_kmac_err_chk.5482362554870217239858923018111947606681201279183526444742829391321382040415
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 5493833740 ps: (rom_ctrl_scoreboard.sv:247) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 5493833740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```