ROM_CTRL/64KB Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: `5fd4ecc0fc`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	18.100s	2.073ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.010s	260.713us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.800s	1.028ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	15.370s	1.032ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.110s	253.093us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.740s	1.037ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.800s	1.028ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.110s	253.093us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	15.140s	3.936ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	14.800s	1.032ms	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.070s	9.938ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	44.720s	2.100ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	31.750s	2.058ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	15.350s	1.362ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	17.600s	1.022ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	17.600s	1.022ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.010s	260.713us	5	5	100.00
		rom_ctrl_csr_rw	14.800s	1.028ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.110s	253.093us	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.410s	264.410us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.010s	260.713us	5	5	100.00
		rom_ctrl_csr_rw	14.800s	1.028ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.110s	253.093us	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.410s	264.410us	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.019m	8.997ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	47.570s	1.702ms	3	20	15.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.769m	1.106ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.664m	2.305ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.769m	1.106ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.019m	8.997ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.019m	8.997ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.019m	8.997ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.019m	8.997ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.019m	8.997ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.769m	1.106ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.769m	1.106ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	18.100s	2.073ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	18.100s	2.073ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	18.100s	2.073ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.664m	2.305ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.019m	8.997ms	50	50	100.00
		rom_ctrl_kmac_err_chk	31.750s	2.058ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.019m	8.997ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.019m	8.997ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.019m	8.997ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	47.570s	1.702ms	3	20	15.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.769m	1.106ms	5	5	100.00
V2S		TOTAL			78	95	82.11
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.993h	81.720ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			408	460	88.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.19	96.89	91.85	97.68	100.00	98.28	97.30	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 22 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.82807335204314822668518166553168222170809861046918048572875724960686864866576
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 116978978 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 116978978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.13274537368283218404346139357888825190663040757247926120186153626137889747066
    Line 438, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17914293767 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 17914293767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 20 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_*' while it is being accessed has 14 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 14 failures.

0.rom_ctrl_passthru_mem_tl_intg_err.109354674052355680932614676920921918875904981473721395990400056511315212110004
Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 695314143 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 695314143 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 695314143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.rom_ctrl_passthru_mem_tl_intg_err.92544322506248651437456108236707433511572712071501125426246964421612773395807
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 2013204720 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 2013204720 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 2013204720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 11 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.100868618018107907955779801667863398510643520328601111649132184645480793360013
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:0c9a06aa-1ed6-4ea0-bd33-5b5f306622a0
```
  - 3.rom_ctrl_stress_all_with_rand_reset.48018201534946560240315915997595732890292469778069262407107663964917924256693
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:9d5d6245-62e2-49c2-a288-86d75d2d474a
```
  - ... and 9 more failures.

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_*' while it is being accessed has 3 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 3 failures.

8.rom_ctrl_passthru_mem_tl_intg_err.90421989837803161039955456405027447703706328866522442303844013644756051442910
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 294025103 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_0' while it is being accessed
  UVM_ERROR @ 294025103 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 294025103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.rom_ctrl_passthru_mem_tl_intg_err.96750508354703697805739395309316461403410674753362918484128074953839613259638
Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 1541546026 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_1' while it is being accessed
  UVM_ERROR @ 1541546026 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 1541546026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (rom_ctrl_base_vseq.sv:91) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 8.rom_ctrl_stress_all_with_rand_reset.55209185931572240785413731344368107906156003932475897443867730819314648837413
    Line 493, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 46830636976 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 46830636976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 17.rom_ctrl_stress_all_with_rand_reset.82380242221497099178398867523428640359967303691711200623101917493995906987102
    Line 457, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 105041140730 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 105041140730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```