ROM_CTRL/64KB Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: `bbf435ceff`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	18.150s	3.031ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.830s	1.788ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.800s	986.437us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.580s	1.017ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	9.930s	1.773ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	14.380s	2.011ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.800s	986.437us	20	20	100.00
		rom_ctrl_csr_aliasing	9.930s	1.773ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	9.900s	497.792us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	14.620s	1.001ms	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	16.630s	1.013ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	53.650s	17.202ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	23.290s	4.944ms	48	50	96.00
V2	alert_test	rom_ctrl_alert_test	15.230s	4.280ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.120s	2.041ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.120s	2.041ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.830s	1.788ms	5	5	100.00
		rom_ctrl_csr_rw	14.800s	986.437us	20	20	100.00
		rom_ctrl_csr_aliasing	9.930s	1.773ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.860s	1.044ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.830s	1.788ms	5	5	100.00
		rom_ctrl_csr_rw	14.800s	986.437us	20	20	100.00
		rom_ctrl_csr_aliasing	9.930s	1.773ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.860s	1.044ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.960m	162.973ms	49	50	98.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	38.840s	2.761ms	3	20	15.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.791m	752.163us	5	5	100.00
		rom_ctrl_tl_intg_err	2.656m	366.094us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.791m	752.163us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.960m	162.973ms	49	50	98.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.960m	162.973ms	49	50	98.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.960m	162.973ms	49	50	98.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.960m	162.973ms	49	50	98.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.960m	162.973ms	49	50	98.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.791m	752.163us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.791m	752.163us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	18.150s	3.031ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	18.150s	3.031ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	18.150s	3.031ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.656m	366.094us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.960m	162.973ms	49	50	98.00
		rom_ctrl_kmac_err_chk	23.290s	4.944ms	48	50	96.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.960m	162.973ms	49	50	98.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.960m	162.973ms	49	50	98.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.960m	162.973ms	49	50	98.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	38.840s	2.761ms	3	20	15.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.791m	752.163us	5	5	100.00
V2S		TOTAL			77	95	81.05
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.493h	127.267ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			406	460	88.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	4	66.67
V2S	4	4	2	50.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.20	96.89	91.99	97.68	100.00	98.28	97.45	98.14

Failure Buckets

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_*' while it is being accessed has 14 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 14 failures.

0.rom_ctrl_passthru_mem_tl_intg_err.41466422836503378538182387679423720184219847398018454308715836903380933096302
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 246365954 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 246365954 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 246365954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.rom_ctrl_passthru_mem_tl_intg_err.49376304120766659579683627895990939014437019816667747487888203409935642122912
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 249564501 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.digest_0' while it is being accessed
  UVM_ERROR @ 249564501 ps: (rom_ctrl_scoreboard.sv:119) [uvm_test_top.env.scoreboard] Check failed (ral.digest[i].predict(kmac_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 249564501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 13 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.92378834114733036186897848399924454961044226610959944514464775247870347062936
    Line 329, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4729597598 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4729597598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.rom_ctrl_stress_all_with_rand_reset.1903318914579240407300797839060597047537281509323591969091635332285510635587
    Line 634, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 81718007460 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 81718007460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 10 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 10 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.82762270696085288338182208841605602322527736189720091784619266675098870094193
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:47749a92-e111-41ed-bdc5-6fb51108c0ca
```
  - 3.rom_ctrl_stress_all_with_rand_reset.104409905650109951724933493094531883561659427271480352934882751036137652716089
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:77a232f1-04ea-436e-9756-ce8d7efd826b
```
  - ... and 8 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 8.rom_ctrl_stress_all_with_rand_reset.108494241891840615990445986107125509022472464180320934032790621879584043526174
    Line 716, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 199373759162 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 199373759162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.rom_ctrl_stress_all_with_rand_reset.22588363982715954686568649597260531386821211410108165838228337877487916342432
    Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 427990384 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 427990384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:247) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 4 failures:
- Test rom_ctrl_kmac_err_chk has 2 failures.
  - 24.rom_ctrl_kmac_err_chk.86829411732438571493473911681541284130451684925459038088017488844689218195029
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 6595580912 ps: (rom_ctrl_scoreboard.sv:247) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 6595580912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.rom_ctrl_kmac_err_chk.81333229870725842610108440539913345079646631208494719701047242798683923187893
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 6589363918 ps: (rom_ctrl_scoreboard.sv:247) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 6589363918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_stress_all has 1 failures.
  - 28.rom_ctrl_stress_all.79510321765244232412687291839164913620120257469756061836911341858342002931041
    Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 17202423417 ps: (rom_ctrl_scoreboard.sv:247) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 17202423417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 37.rom_ctrl_corrupt_sig_fatal_chk.75089180185797267321053943187747413181853600778983128966114076707843925652751
    Line 293, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 64832189312 ps: (rom_ctrl_scoreboard.sv:247) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 64832189312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_*' while it is being accessed has 3 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 3 failures.

5.rom_ctrl_passthru_mem_tl_intg_err.3430458990177286256143496136187046199130515776604093471926647514577395682017
Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 2145739108 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_3' while it is being accessed
  UVM_ERROR @ 2145739108 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 2145739108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.rom_ctrl_passthru_mem_tl_intg_err.23725771095103298587338547898713083385966039403106518852501372168875121587984
Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 2240424331 ps: (uvm_reg.svh:2019) [RegModel] Trying to predict value of register 'rom_ctrl_regs_reg_block.exp_digest_0' while it is being accessed
  UVM_ERROR @ 2240424331 ps: (rom_ctrl_scoreboard.sv:120) [uvm_test_top.env.scoreboard] Check failed (ral.exp_digest[i].predict(expected_digest[i*TL_DW+:TL_DW]))
  UVM_INFO @ 2240424331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 16.rom_ctrl_stress_all_with_rand_reset.14734302864864601953221891168742159367091475533252340188430854877488233446841
    Line 259, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1455509425 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 1455509425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 26.rom_ctrl_stress_all_with_rand_reset.27244481503993703960089875056464875232550433926920544637200001110081088122403
    Line 259, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1532786001 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 1532786001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:91) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 6.rom_ctrl_stress_all_with_rand_reset.3191983018326712232663682092503145639895191699738695252002034994318723526802
    Line 307, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4326166185 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 4326166185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```