3707c48f56| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 16.870s | 1.047ms | 10 | 10 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 17.390s | 1.037ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 10.090s | 1.775ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 14.170s | 1.751ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 10.000s | 274.513us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 16.080s | 4.337ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 10.090s | 1.775ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 10.000s | 274.513us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 10.110s | 915.957us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 8.350s | 688.562us | 5 | 5 | 100.00 |
| V1 | TOTAL | 75 | 75 | 100.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 16.740s | 1.039ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 59.750s | 1.313ms | 50 | 50 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 32.870s | 7.847ms | 50 | 50 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 15.660s | 1.039ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 19.090s | 4.082ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 19.090s | 4.082ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 17.390s | 1.037ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 10.090s | 1.775ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 10.000s | 274.513us | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 18.500s | 2.018ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 17.390s | 1.037ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 10.090s | 1.775ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 10.000s | 274.513us | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 18.500s | 2.018ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 8.332m | 79.859ms | 49 | 50 | 98.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 1.586m | 12.154ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 3.823m | 2.372ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 2.654m | 1.107ms | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 3.823m | 2.372ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.332m | 79.859ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.332m | 79.859ms | 49 | 50 | 98.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 8.332m | 79.859ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.332m | 79.859ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.332m | 79.859ms | 49 | 50 | 98.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 3.823m | 2.372ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 3.823m | 2.372ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 16.870s | 1.047ms | 10 | 10 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 16.870s | 1.047ms | 10 | 10 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 16.870s | 1.047ms | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 2.654m | 1.107ms | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 8.332m | 79.859ms | 49 | 50 | 98.00 |
| rom_ctrl_kmac_err_chk | 32.870s | 7.847ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 8.332m | 79.859ms | 49 | 50 | 98.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.332m | 79.859ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 8.332m | 79.859ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 1.586m | 12.154ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 3.823m | 2.372ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 94 | 95 | 98.95 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.860h | 110.897ms | 18 | 50 | 36.00 |
| V3 | TOTAL | 18 | 50 | 36.00 | |||
| TOTAL | 427 | 460 | 92.83 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 4 | 4 | 3 | 75.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.16 | 96.89 | 91.85 | 97.68 | 100.00 | 98.28 | 97.30 | 98.14 |
UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:
0.rom_ctrl_stress_all_with_rand_reset.41304064956050314709642468258707515220736681936323387970666168184211192093508
Line 468, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 61313875042 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 61313875042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rom_ctrl_stress_all_with_rand_reset.48091517787000001562923915160570411699145206459668333482600308483116751730674
Line 1133, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 66878276822 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 66878276822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 13 failures:
1.rom_ctrl_stress_all_with_rand_reset.74406077946377170133363846632701166150132611294579085127752440456488872083315
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:0e14c8e1-d14a-46fd-a95e-cfb496de0aac
3.rom_ctrl_stress_all_with_rand_reset.105831702651142067738764269160949329219181762512961421456240177926456165365141
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:8142383a-223c-4fab-8dd4-629382e0176a
... and 11 more failures.
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 5 failures:
12.rom_ctrl_stress_all_with_rand_reset.49138237073668399210182190189365299249782065923312872159220948756451460820119
Line 325, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 18681304346 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 18681304346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.rom_ctrl_stress_all_with_rand_reset.30628616329427741732822303489135129849460992346307701197880950091835417152014
Line 397, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 11624193474 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
UVM_INFO @ 11624193474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 1 failures:
8.rom_ctrl_stress_all_with_rand_reset.50802331203523368640137961108759897875317976632466970630168835748270015500877
Line 588, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 71187037751 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
UVM_INFO @ 71187037751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:254) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
12.rom_ctrl_corrupt_sig_fatal_chk.23014732524859957172349193938343555917780960968642326057320594707651448710486
Line 291, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 59178411027 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 59178411027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---