ROM_CTRL/64KB Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	20.170s	1.009ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.070s	265.655us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.870s	1.420ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	10.540s	1.030ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.200s	251.172us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	11.810s	984.051us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.870s	1.420ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.200s	251.172us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	10.140s	1.032ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	9.750s	260.713us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.030s	3.950ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	46.050s	1.035ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	32.860s	4.018ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	15.260s	4.478ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	15.110s	257.642us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	15.110s	257.642us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.070s	265.655us	5	5	100.00
		rom_ctrl_csr_rw	14.870s	1.420ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.200s	251.172us	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.750s	4.113ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.070s	265.655us	5	5	100.00
		rom_ctrl_csr_rw	14.870s	1.420ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.200s	251.172us	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.750s	4.113ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.697m	107.895ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.595m	24.761ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.796m	1.474ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.725m	1.145ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.796m	1.474ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.697m	107.895ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.697m	107.895ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.697m	107.895ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.697m	107.895ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.697m	107.895ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.796m	1.474ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.796m	1.474ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	20.170s	1.009ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	20.170s	1.009ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	20.170s	1.009ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.725m	1.145ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.697m	107.895ms	50	50	100.00
		rom_ctrl_kmac_err_chk	32.860s	4.018ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.697m	107.895ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.697m	107.895ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.697m	107.895ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.595m	24.761ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.796m	1.474ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.609h	24.999ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			430	460	93.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.19	96.89	91.85	97.68	100.00	98.28	97.30	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 13 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.68517303565575242022467857647559711361912867922176471566599565332767928629444
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 110362628 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 110362628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rom_ctrl_stress_all_with_rand_reset.42362525493983331842840152750612641468279129432623250029483821917782592130712
    Line 290, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2423318434 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2423318434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 10 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 10 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.16722114820140549359876532710174189234291818975490662859659752578870613861998
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:270f7462-8af7-48e8-872e-f855758eb786
```
  - 4.rom_ctrl_stress_all_with_rand_reset.98180107311552234621496163197829890497047280828743786624646757167979765130451
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:b6c7d6ac-c897-4313-b949-65993c371ff5
```
  - ... and 8 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 4 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 4 failures.
  - 7.rom_ctrl_stress_all_with_rand_reset.65575215110695644362451252822113520133797093519515532006841190880684387780859
    Line 273, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2484603757 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 2484603757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.rom_ctrl_stress_all_with_rand_reset.531611831538154482801917939124260671775273346883902093772734151828973640305
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 672305827 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 672305827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:91) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 14.rom_ctrl_stress_all_with_rand_reset.35646095603719120240489021029980700407723266617207977735889660757663112495659
    Line 378, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 51184245829 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 51184245829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.rom_ctrl_stress_all_with_rand_reset.1439419841979505322006161421713703344338966900638929435955503834617720769194
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1167519998 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1167519998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:254) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 41.rom_ctrl_stress_all_with_rand_reset.45954192519107901723221523776631513553082328652287506944645425177129363753472
    Line 652, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 882445076243 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 882445076243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `07b417ef03`