ROM_CTRL/64KB Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	12.640s	266.604us	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	18.320s	1.030ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	10.070s	262.472us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	10.250s	258.756us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.130s	991.697us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.130s	2.172ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	10.070s	262.472us	20	20	100.00
		rom_ctrl_csr_aliasing	10.130s	991.697us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	10.060s	1.032ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	9.900s	1.452ms	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.580s	996.612us	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.131m	36.303ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	34.100s	3.932ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	15.160s	986.167us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	17.570s	4.131ms	19	20	95.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	17.570s	4.131ms	19	20	95.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	18.320s	1.030ms	5	5	100.00
		rom_ctrl_csr_rw	10.070s	262.472us	20	20	100.00
		rom_ctrl_csr_aliasing	10.130s	991.697us	5	5	100.00
		rom_ctrl_same_csr_outstanding	13.740s	895.712us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	18.320s	1.030ms	5	5	100.00
		rom_ctrl_csr_rw	10.070s	262.472us	20	20	100.00
		rom_ctrl_csr_aliasing	10.130s	991.697us	5	5	100.00
		rom_ctrl_same_csr_outstanding	13.740s	895.712us	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.685m	154.752ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.101m	8.886ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.778m	352.763us	5	5	100.00
		rom_ctrl_tl_intg_err	2.657m	4.341ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.778m	352.763us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.685m	154.752ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.685m	154.752ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.685m	154.752ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.685m	154.752ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.685m	154.752ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.778m	352.763us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.778m	352.763us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	12.640s	266.604us	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	12.640s	266.604us	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	12.640s	266.604us	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.657m	4.341ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.685m	154.752ms	50	50	100.00
		rom_ctrl_kmac_err_chk	34.100s	3.932ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.685m	154.752ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.685m	154.752ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.685m	154.752ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.101m	8.886ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.778m	352.763us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.986h	29.256ms	9	50	18.00
V3		TOTAL			9	50	18.00
		TOTAL			418	460	90.87

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.29	96.89	91.99	97.68	100.00	98.62	97.45	98.37

Failure Buckets

Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 22 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 22 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.88771940961412957263129687436146962812187259536163352365597147193539174362729
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:bd206b4f-dcd2-475f-9c35-253562df7ead
```
  - 2.rom_ctrl_stress_all_with_rand_reset.25794162861440059598317372828862104244986328409273890679318556409740610698137
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:df65bdcb-7a15-42e7-9870-d5a3abf725c7
```
  - ... and 20 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 14 failures.
  - 3.rom_ctrl_stress_all_with_rand_reset.57943760578572990412838458821533564768279932576985812070298254113706144952947
    Line 266, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 413712918 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 413712918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.rom_ctrl_stress_all_with_rand_reset.67969243123418700473127285055338436586822393678197004590305067128493522634423
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 215224453 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 215224453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:91) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 6.rom_ctrl_stress_all_with_rand_reset.34820926143157181388569008742260211595327196026039888842460707666873118499382
    Line 277, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1704353829 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1704353829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.rom_ctrl_stress_all_with_rand_reset.38658884941932405209752847208863964740444749845898506542099813190525069658648
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 260172007 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 260172007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 11.rom_ctrl_stress_all_with_rand_reset.54475398885164945287599681872614616788190688071778278162626626900953055728508
    Line 330, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20682766304 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 20682766304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.rom_ctrl_stress_all_with_rand_reset.63017368634936156194081173254385250423738034644844745920549267189759225933034
    Line 543, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 97929822004 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 97929822004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:254) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_tl_errors has 1 failures.
  - 0.rom_ctrl_tl_errors.103893429849886968573206497809420795886715566899786429357897799107518677935983
    Line 253, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_tl_errors/latest/run.log
```
  UVM_ERROR @ 3290056777 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 3290056777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 14.rom_ctrl_stress_all_with_rand_reset.37365171641201143558531079057142838970749269090699318055518953298617107038154
    Line 288, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3041330848 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 3041330848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `07b417ef03`