ROM_CTRL/64KB Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	12.860s	268.136us	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.290s	1.497ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.280s	986.785us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	15.050s	8.865ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	14.510s	984.923us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.340s	1.066ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.280s	986.785us	20	20	100.00
		rom_ctrl_csr_aliasing	14.510s	984.923us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	9.950s	986.155us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	10.130s	883.732us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.390s	4.133ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	53.070s	11.969ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	33.040s	4.027ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	15.230s	989.981us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	14.600s	1.073ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	14.600s	1.073ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.290s	1.497ms	5	5	100.00
		rom_ctrl_csr_rw	14.280s	986.785us	20	20	100.00
		rom_ctrl_csr_aliasing	14.510s	984.923us	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.560s	985.166us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.290s	1.497ms	5	5	100.00
		rom_ctrl_csr_rw	14.280s	986.785us	20	20	100.00
		rom_ctrl_csr_aliasing	14.510s	984.923us	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.560s	985.166us	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.484m	17.491ms	48	50	96.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.120m	3.119ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.785m	658.584us	5	5	100.00
		rom_ctrl_tl_intg_err	2.687m	6.713ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.785m	658.584us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.484m	17.491ms	48	50	96.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.484m	17.491ms	48	50	96.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.484m	17.491ms	48	50	96.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.484m	17.491ms	48	50	96.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.484m	17.491ms	48	50	96.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.785m	658.584us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.785m	658.584us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	12.860s	268.136us	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	12.860s	268.136us	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	12.860s	268.136us	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.687m	6.713ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.484m	17.491ms	48	50	96.00
		rom_ctrl_kmac_err_chk	33.040s	4.027ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.484m	17.491ms	48	50	96.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.484m	17.491ms	48	50	96.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.484m	17.491ms	48	50	96.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.120m	3.119ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.785m	658.584us	5	5	100.00
V2S		TOTAL			93	95	97.89
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.026h	40.696ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			423	460	91.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.31	96.89	92.13	97.68	100.00	98.62	97.45	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 18 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.50265017076322437532745807685668829476253130637509882975854217949868253715885
    Line 354, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 49050675326 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 49050675326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.rom_ctrl_stress_all_with_rand_reset.56766275146356033879591501216258181093059795242360844536590074911766747190948
    Line 388, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 51458358867 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 51458358867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 16 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 13 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 13 failures.
  - 3.rom_ctrl_stress_all_with_rand_reset.103322420068680232880379529185119648028580922644011488993258897085182999042410
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c96fde10-92da-4315-b258-33651538cbd3
```
  - 8.rom_ctrl_stress_all_with_rand_reset.23601603424940291703148958018487846947788016498690844064772128155214056535744
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:3e6858ca-fe0e-4d3f-8ad9-9220351bb2a7
```
  - ... and 11 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 4 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 4 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.53275769879310568320013760240219703807321440145950848546122403504427803432124
    Line 310, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 29624026513 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 29624026513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.rom_ctrl_stress_all_with_rand_reset.99134249792592900172890812556474052376510311090390303413564272071651293478308
    Line 352, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 176086166063 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 176086166063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:254) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 2 failures.
  - 10.rom_ctrl_corrupt_sig_fatal_chk.82111752788976362600689851728515057874449925658566934985365456006938436451766
    Line 293, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 71681160559 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 71681160559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.rom_ctrl_corrupt_sig_fatal_chk.72203901621467864696862733717292167827521378687769850507689426107761567916363
    Line 284, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 46616525362 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 46616525362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `07b417ef03`