ROM_CTRL/64KB Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: `c082b8981f`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	17.640s	1.052ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.460s	2.093ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.040s	990.598us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	10.460s	593.350us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	14.380s	991.438us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.000s	2.025ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.040s	990.598us	20	20	100.00
		rom_ctrl_csr_aliasing	14.380s	991.438us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	9.740s	506.214us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	10.010s	988.998us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.470s	7.147ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	57.640s	37.197ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	33.640s	2.059ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	15.260s	4.275ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	15.220s	250.055us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	15.220s	250.055us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.460s	2.093ms	5	5	100.00
		rom_ctrl_csr_rw	15.040s	990.598us	20	20	100.00
		rom_ctrl_csr_aliasing	14.380s	991.438us	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.480s	1.125ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.460s	2.093ms	5	5	100.00
		rom_ctrl_csr_rw	15.040s	990.598us	20	20	100.00
		rom_ctrl_csr_aliasing	14.380s	991.438us	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.480s	1.125ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	6.732m	29.631ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.585m	21.994ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.148m	1.231ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.691m	491.862us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.148m	1.231ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.732m	29.631ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.732m	29.631ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	6.732m	29.631ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.732m	29.631ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.732m	29.631ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.148m	1.231ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.148m	1.231ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	17.640s	1.052ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	17.640s	1.052ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	17.640s	1.052ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.691m	491.862us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	6.732m	29.631ms	50	50	100.00
		rom_ctrl_kmac_err_chk	33.640s	2.059ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	6.732m	29.631ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.732m	29.631ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	6.732m	29.631ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.585m	21.994ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.148m	1.231ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	3.251m	6.591ms	1	50	2.00
V3		TOTAL			1	50	2.00
		TOTAL			410	460	89.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.22	96.89	91.85	97.68	100.00	98.28	97.45	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:848) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 25 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.12442574556011362445367068915209058491227640601721353242624186327978952862336
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 443114254 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 443114254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rom_ctrl_stress_all_with_rand_reset.97594782252600588771116956994628946054123075766966486597171252898776932468804
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 105846111 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 105846111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:91) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 17 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 17 failures.
  - 9.rom_ctrl_stress_all_with_rand_reset.9535867722331099433860901366207099774715714306340426203380266701633027365624
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 339352809 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 339352809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.rom_ctrl_stress_all_with_rand_reset.39327594375468734316663980432883401906321320168274759463627438267506678449917
    Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  15426040 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @  15426040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.18885658281896286320812469754497019537089254345121355773813367241215769622653
    Line 259, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1315557761 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1315557761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.rom_ctrl_stress_all_with_rand_reset.101888413076803570666146171133549569754001824313612240241105192039625216603823
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 703674303 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 703674303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:254) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_stress_all has 1 failures.
  - 8.rom_ctrl_stress_all.47650587751681279682154010904213843214469335932502409174746553480695610107154
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 5985489640 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 5985489640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: c082b8981f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c082b8981f`