ROM_CTRL/64KB Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: `098010d125`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	12.820s	943.136us	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.540s	265.907us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.920s	1.971ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	10.270s	253.296us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.050s	250.407us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	11.830s	1.061ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.920s	1.971ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.050s	250.407us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	9.860s	444.193us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	10.050s	3.093ms	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.160s	1.022ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	57.130s	4.507ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	31.420s	8.574ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	15.430s	1.016ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.540s	2.141ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.540s	2.141ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.540s	265.907us	5	5	100.00
		rom_ctrl_csr_rw	14.920s	1.971ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.050s	250.407us	5	5	100.00
		rom_ctrl_same_csr_outstanding	13.930s	496.232us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.540s	265.907us	5	5	100.00
		rom_ctrl_csr_rw	14.920s	1.971ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.050s	250.407us	5	5	100.00
		rom_ctrl_same_csr_outstanding	13.930s	496.232us	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.284m	8.088ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.622m	27.029ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.861m	572.293us	5	5	100.00
		rom_ctrl_tl_intg_err	2.775m	1.764ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.861m	572.293us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.284m	8.088ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.284m	8.088ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.284m	8.088ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.284m	8.088ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.284m	8.088ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.861m	572.293us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.861m	572.293us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	12.820s	943.136us	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	12.820s	943.136us	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	12.820s	943.136us	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.775m	1.764ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.284m	8.088ms	50	50	100.00
		rom_ctrl_kmac_err_chk	31.420s	8.574ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.284m	8.088ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.284m	8.088ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.284m	8.088ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.622m	27.029ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.861m	572.293us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.605m	10.781ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			409	460	88.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.48	96.65	88.34	97.68	100.00	96.90	97.45	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 31 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.96877977373998510833482932775878672505695300719530848999355759877454173597898
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 218928099 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 218928099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rom_ctrl_stress_all_with_rand_reset.98121890373436362899250103271983664769053523442532923268608026537591330971137
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 202350233 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 202350233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 29 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:91) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 16 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 16 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.59277214257123094677416497405621773152174086729861488629228794744886958248749
    Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  46679966 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @  46679966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rom_ctrl_stress_all_with_rand_reset.40335801840620446131062932851687293181931679070527495120134264848556044848390
    Line 286, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3810184821 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 3810184821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 21.rom_ctrl_stress_all_with_rand_reset.93961482791787929752542466814890747534627209873082122444378711715192308925379
    Line 316, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10489825104 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 10489825104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.rom_ctrl_stress_all_with_rand_reset.99924361200842431347943442700520426241315975199524637539732048999998462994557
    Line 312, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26201439993 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 26201439993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:254) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_kmac_err_chk has 1 failures.
  - 22.rom_ctrl_kmac_err_chk.86250081874123831538897948830286063631135243831183489940839157450999271282633
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 8205907254 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 8205907254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: 098010d125

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `098010d125`