ROM_CTRL/64KB Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: `584c3d46af`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	18.420s	4.102ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	18.530s	1.035ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.180s	2.060ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	15.090s	1.831ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.180s	255.036us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.150s	4.095ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.180s	2.060ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.180s	255.036us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	10.000s	2.059ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	15.260s	981.636us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	12.700s	266.251us	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	50.670s	3.990ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	33.750s	39.469ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	15.490s	1.024ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	14.510s	1.031ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	14.510s	1.031ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	18.530s	1.035ms	5	5	100.00
		rom_ctrl_csr_rw	15.180s	2.060ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.180s	255.036us	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.690s	4.148ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	18.530s	1.035ms	5	5	100.00
		rom_ctrl_csr_rw	15.180s	2.060ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.180s	255.036us	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.690s	4.148ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	6.873m	27.523ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.088m	6.296ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.792m	1.895ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.727m	2.281ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.792m	1.895ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.873m	27.523ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.873m	27.523ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	6.873m	27.523ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.873m	27.523ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.873m	27.523ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.792m	1.895ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.792m	1.895ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	18.420s	4.102ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	18.420s	4.102ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	18.420s	4.102ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.727m	2.281ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	6.873m	27.523ms	50	50	100.00
		rom_ctrl_kmac_err_chk	33.750s	39.469ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	6.873m	27.523ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.873m	27.523ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	6.873m	27.523ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.088m	6.296ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.792m	1.895ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.427m	2.120ms	1	50	2.00
V3		TOTAL			1	50	2.00
		TOTAL			411	460	89.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.16	96.89	91.85	97.68	100.00	98.28	97.30	98.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 25 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.94449586656480098212270591527311896181487720887962222435294717765788509890951
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 202865995 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 202865995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.49524106432140074147337654226099126593299711179816668934823569313212767656083
    Line 270, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 734684608 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 734684608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:91) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 21 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 21 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.29764752361167845668817656355151903337905050501964359433929279331148993692191
    Line 274, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1054149465 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1054149465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rom_ctrl_stress_all_with_rand_reset.34427530983694713659854043008722335931685425497672175371181336503255249331215
    Line 271, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 515060061 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 515060061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 13.rom_ctrl_stress_all_with_rand_reset.42711495694901580890140315384323838006220559761704366569199594465299654043802
    Line 270, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6838010712 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 6838010712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.rom_ctrl_stress_all_with_rand_reset.95493993547445464877893870947624622788029484058028063997077378588964511711101
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 253963404 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 253963404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

ROM_CTRL/64KB Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: 584c3d46af

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `584c3d46af`