ROM_CTRL/64KB Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: d09e282b26

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 16.480s 1.057ms 10 10 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 16.700s 3.139ms 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 13.280s 4.103ms 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 9.510s 260.533us 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 13.120s 3.977ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 14.740s 9.140ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 13.280s 4.103ms 20 20 100.00
rom_ctrl_csr_aliasing 13.120s 3.977ms 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 9.360s 1.074ms 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 9.450s 1.030ms 5 5 100.00
V1 TOTAL 75 75 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 14.990s 1.025ms 50 50 100.00
V2 stress_all rom_ctrl_stress_all 46.300s 1.479ms 50 50 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 29.830s 13.119ms 50 50 100.00
V2 alert_test rom_ctrl_alert_test 14.030s 1.219ms 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 14.900s 518.091us 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 14.900s 518.091us 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 16.700s 3.139ms 5 5 100.00
rom_ctrl_csr_rw 13.280s 4.103ms 20 20 100.00
rom_ctrl_csr_aliasing 13.120s 3.977ms 5 5 100.00
rom_ctrl_same_csr_outstanding 13.510s 268.349us 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 16.700s 3.139ms 5 5 100.00
rom_ctrl_csr_rw 13.280s 4.103ms 20 20 100.00
rom_ctrl_csr_aliasing 13.120s 3.977ms 5 5 100.00
rom_ctrl_same_csr_outstanding 13.510s 268.349us 20 20 100.00
V2 TOTAL 240 240 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 7.957m 9.810ms 50 50 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 1.444m 6.072ms 20 20 100.00
V2S tl_intg_err rom_ctrl_sec_cm 3.838m 1.531ms 5 5 100.00
rom_ctrl_tl_intg_err 2.617m 505.625us 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 3.838m 1.531ms 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 7.957m 9.810ms 50 50 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 7.957m 9.810ms 50 50 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 7.957m 9.810ms 50 50 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 7.957m 9.810ms 50 50 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 7.957m 9.810ms 50 50 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 3.838m 1.531ms 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 3.838m 1.531ms 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 16.480s 1.057ms 10 10 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 16.480s 1.057ms 10 10 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 16.480s 1.057ms 10 10 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 2.617m 505.625us 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 7.957m 9.810ms 50 50 100.00
rom_ctrl_kmac_err_chk 29.830s 13.119ms 50 50 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 7.957m 9.810ms 50 50 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 7.957m 9.810ms 50 50 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 7.957m 9.810ms 50 50 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 1.444m 6.072ms 20 20 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 3.838m 1.531ms 5 5 100.00
V2S TOTAL 95 95 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 4.959m 5.233ms 49 50 98.00
V3 TOTAL 49 50 98.00
TOTAL 459 460 99.78

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.47 96.89 92.28 97.68 100.00 98.62 97.75 99.06

Failure Buckets

Past Results